Physically Unclonable Function (PUF) circuits are designed to provide part-specific responses that random across different copies of the circuit by exploiting unavoidable process variations in nanometer scale fabrication. This property can be used as an important building block security and cryptographic applications including key generation challenge-response authentication. A major problem, however, is ensure PUF response stability reliability presence environmental noise. SRAM based PUFs...

The test generation problem for analog/RF circuits has been largely intractable due to the fact that repetitive circuit simulation stimulus optimization is extremely time-consuming. As a consequence, it difficult, if not impossible, generate tests practical mixed-signal/RF include effects of tester inaccuracies and measurement noise. To offset this allow scale different applications, we propose new approach in which FSM models are abstracted from hardware measurements on fabricated devices....

The proliferation of third-party silicon manufacturing has increased the vulnerability integrated circuits to malicious insertion hardware for purpose leaking secret information or even rendering useless while deployed in field. A key goal is detect presence such before they are activated subversive reasons. One way achieve this parasitic loads on internal nodes a victim circuit. However, detection becomes difficult normal process variations itself. In work, we show how high-resolution...

As silicon integration complexity increases with 3D stacking and Through-Silicon-Via (TSV), so does the occurrence of memory IO defects associated test validation time. This ultimately leads to an overall cost increase. On a 14nm Intel SOC, reusable BIST engine called Converged-Pattern-Generator-Checker (CPGC) are architected detect defects, combined software assisted repair technology automatically cell on stacked Wide-IO DRAM. Additionally, we also present CPGC gate count, power,...

This paper presents a new fully automated design methodology for analog circuit synthesis in submicron technology. It requires topology and desired performance as input it produces not only the sized netlist but also layout of components. Today's technology accompanies appreciable process variation. In conventional equation based sizing technique there is high chance that optimized point at boundary feasible space. Due to variation may fall outside space some specifications are meet after...

As RF design scales to the 28nm technology node and beyond, pre-silicon simulation verification of complex mixed-signal/RF SoCs is becoming intractable due difficulties associated with simulating diverse electrical effects bugs. a consequence, there increasing pressure develop comprehensive post-silicon test debug tools that can be used identify bugs improve modeling nonidealities observed in silicon. Often, it not known a-priori what these are how they modeled, significantly complicating...

Alternative signature based testing of analog/RF circuits and systems has been established over the last two decades. Signature is predicated on from device under test (DUT) to statistically predict specifications an IC. Statistical correlation between are built a set initial ICs. Aliasing in space will produce aliasing specification lead incorrect prediction. Alternate aims create unique IC specific avoid aliasing. Hardware security also entails be authenticated. Theories infrastructure...

With trends in mixed-signal systems-on-chip indicating increasingly extreme scaling of device dimensions and higher levels integration, the tasks both design validation is becoming complex. Post-silicon mixed-signal/RF systems provides assurances functionality complex that cannot be asserted by even some most advanced simulators. We introduce RAVAGE (from “random;” “validation;” “generation”), an algorithm for generating stimuli post-silicon systems. The approach new no assumption made about...

Due to the use of scaled technologies, high levels integration and speeds today's mixed-signal SoCs, problem validating correct operation SoC under electrical bugs that debugging yield loss due unmodeled multi-dimensional variability effects is extremely challenging. Precise simulation all aspects design including interfaces between digital analog circuitry, coupling across power ground planes, crosstalk, etc., process corners very hard achieve in a practical sense. The expected get worse as...

Insertion of malicious Trojans into outsourced chip manufacturing generally results in increased capacitances internal circuit nodes that have been tapped for node controllability and observability by circuitry. Current path delay measurement side channel Trojan detection techniques are unable to detect present low loading such nodes, especially the presence large process variations. In this paper, a high-resolution method digital logic based on pulse propagation is developed. The exhibits...

Post-silicon validation of RF/mixed-signal circuits is challenging due to the need excite all possible operational modes DUT in order establish equivalence between its specified and observed behaviors ensure that does not produce any unexpected can lead system failure. In this research, we first develop a methodology for determining if contains are explicitly included behavioral model. A complex (optimized) test waveform applied response signature captured. It seen presence behaviors,...

In production testing of analog/RF ICs, application standard specification-based tests for IC classification is not always an attractive option due to the high costs and test times involved. this paper, a new generation algorithm first developed that has property corresponding DUT response signatures devices from diverse process corners are maximally separable. other words, space can be partitioned into large number partitions each tested uniquely diagnosed lie in one such partition its...

In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit randomness silicon manufacturing processes to create IC-specific signatures for authentication. While prior PUF largely digital, this work we propose novel design based on transfer function variability an analog push-pull amplifier under process variations. A differential architecture is with digital interfaces allow be used...

Future 5G wireless systems will deploy massive MIMO with large numbers of transmit and receive antennas novel RF transceiver architectures that admit beamforming. Such need to be designed built-in test post-manufacture self-tuning capability for yield enhancement in-field tuning. A key issue is the lack observability into internal circuit nodes due convergence multiple beamforming chains a combined baseband signal decouple individual chain behaviors from signals. second problem testing...

High levels of integration in SoCs and SoPs is making pre as well post-silicon validation mixed-signal systems increasingly difficult due to: (a) lack automated postsilicon design checking algorithms (b) controllability observability internal circuit nodes post-silicon. While digital scan chains provide states, analog suffer from signal integrity, bandwidth loading issues. In this paper, we propose a novel technique based on built-in state consistency that allows both mixed-signal/RF without...

Outsourcing of chip manufacturing to untrusted foundries and using third party IPs in design, have opened the possibility inserting malicious hardware Trojans into circuit. As excitation Trojan is extremely rare, it almost impossible detect with functional logic testing. We need without actually activating (side channel analysis). Hardware circuit get inputs from low transition probability nodes original Tapping these for creating increase capacitive load at those nodes. developed a very...

We present a methodology for algorithmic generation of test signals the detection and diagnosis variety short open-circuit defects in analog circuits. Prior algorithms have focused on known or open defect values. This places burden failure coverage accurate analysis observed failed parts at high cost. In this work, we optimize stimulus to detect <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">weakest</i> shorts opens circuits using concurrent...

Testing of radio frequency (RF) components such as mixers, amplifiers and voltage controlled oscillators (VCO) traditionally relies on the ability to accurately estimate device characteristics using down conversion or undersampling based test setups. Efficient accurate acquisition modulating signal either requires a phase locked local oscillator is limited in accuracy. This makes setup more complicated hence costly. In this paper novel low cost setup, independent requirement any synchronous...

In the modern mixed-signal SoC design cycle, designers are frequently tasked with detecting and diagnosing behavioral discrepancies between descriptions given at different levels of hierarchy, e.g. vs. transistor level or behavioral/transistor fabricated silicon. One problem is detection, to determine if differences exist. If such (anomalies) detected, then diagnosis concerned identifying module in a hierarchical description system that most likely root cause anomaly (typically under...

Recent studies show that increasing numbers of design bugs are escaping to post-silicon due the complexity advanced designs and lack adequate verification tools can validate complex electrical interactions between subsystems on an integrated circuit. In this paper, we present a novel tool for validation mixed-signal/RF circuits through cooperative test stimulus generation behavior-learning. The implemented technique leverages iterative supervised learning techniques comprehensively diagnose...

Technology scaling along with unprecedented levels of device integration has led to increasing numbers analog/mixed-signal/RF design bugs escaping into silicon. Such are manifested under specific system-on-chip (SoC) operating conditions and their effects difficult predict a-priori. This paper describes recent advances in detecting diagnosing such using "guided" stochastic test stimulus generation algorithms. A key challenge is that unlike traditional for manufacturing predicated on known...