A5034004697- Interconnection Networks and Systems
- Software-Defined Networks and 5G
- Advanced Optical Network Technologies
- Advanced Graph Theory Research
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Cloud Computing and Resource Management
- Caching and Content Delivery
- Parallel Computing and Optimization Techniques
- Peer-to-Peer Network Technologies
- Distributed systems and fault tolerance
- Silicon Carbide Semiconductor Technologies
- Radiation Effects in Electronics
- Graph theory and applications
- VLSI and FPGA Design Techniques
- Complex Network Analysis Techniques
- Embedded Systems Design Techniques
- Ferroelectric and Negative Capacitance Devices
- Graphene research and applications
- Graph Theory and Algorithms
- DNA and Biological Computing
- Cooperative Communication and Network Coding
- graph theory and CDMA systems
- Optimization and Packing Problems
- VLSI and Analog Circuit Testing
Soochow University
2015-2024
Xiamen University of Technology
2023
Novelis (Canada)
2016
Hohai University
2012
National Aviation University
2009
Motorola (United States)
1999-2002
University of California, Los Angeles
1996-1999
Colorado School of Mines
1999
Tsinghua University
1998
The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range dielectric permittivities using two-dimensional (2-D) simulator implemented with quantum mechanical models. It found that the degradation caused by fringing fields from to source/drain regions. These in regions further induce electric channel which weakens control. thickness-to-length aspect ratio proper parameter quantify percentage field and thus short degradation. In...
Abstract Connectivity is a classic measure for reliability of multiprocessor system in the case processor failures. Extra connectivity and component are two important indicators presence failing processors. The $h$-extra $\kappa _{h}(G)$ graph $G$ minimum number nodes whose removal will disconnect $G$, every remaining has at least $h+1$ nodes. Moreover, $h$-component $c\kappa deletion results with $h$ components. However, extra many well-known networks have been independently investigated....
A set of spanning trees T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ; xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ;. .. Tk in a network G are Completely Independent Spanning Trees (CISTs) if for any two nodes u and v V (G), the paths between have no common edges internal nodes. CISTs important applications data center networks, such as fault-tolerant multi-node broadcasting, one-to-all reliable secure message distribution,...
The generalized hypercube (GH) is one key interconnection network with excellent topological properties. It contains many other topologies, such as the network, complete graph, mesh and k-ary n-cube network. can also be used to construct some data center networks, HyperX, BCube, FBFLY, SWCube. However, construction cost of GH high since it too links. In this paper, we propose a novel low architecture called exchanged (EGH). We study properties EGH, number edges, degree vertices,...
Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results study the effect large angle V/sub T/ adjust implant parameters on performance hot carrier reliability. Results both conventionally doped single have been presented for comparison purposes.
In recent years, there are many new findings on independent spanning trees (ISTs for short) in hypercubes, crossed cubes, locally twisted and Mobius which all belong to a more general network category called bijective connection networks (BC networks). However, little progress has been made ISTs BC networks. this paper, we first propose the definitions of conditional V -dimensional-permutation. We then give linear parallel algorithm rooted at an arbitrary vertex networks, include based...
We explore four different technology and design options for transistors library cells a low power supply voltage of 0.4 V circuit statistics representative artificial intelligence (AI) applications. The rules correspond to 2nm node with cell heights 100~110 nm 30 gate pitch. Holistic analysis the RO (Ring Oscillator) behavior, including MOL parasitics, all major variability sources, stress proximity effects suggests that FinFET nanoslab transistor exhibit wide range performance differences....
Fault-tolerance is an important parameter to measure the performance of a network. However, most works only consider fault single vertex and ignore structure-fault The generalized hypercube G(mr,mr−1,…,m1) one key interconnection network with excellent topological properties. In this paper, we study H-structure fault-tolerance by studying its connectivity H-substructure for H∈{K1,M,C3,C4,K4}. Since can be used construct some data center networks, such as BCube, HyperX, FBFLY, results in...