Two fundamental oscillators, a 240 GHz and 272 are demonstrated using the IBM CMOS 32 nm process. The design of both oscillators was based on Colpitts differential topology, where parasitic capacitances device used as part inductor-capacitor tank. process consideration is discussed, well measurement procedures. A simplified model predicting output power voltage-controlled oscillator (VCO) its phase noise presented, comparison to measured results discussed. An level 0.2 mW ( <formula...

A new topology of a low-power F-band reflection amplifier for active reflectarrays is proposed and demonstrated using CMOS fully depleted silicon-on-insulator 28-nm process. The design enables frequency response center tuning, as well phase control the reflected signal. chip consumes core area only 90 × 80 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> incorporated into 2 printed reflectarray antenna, implementing first co-polarized...

A reflectarray antenna, based on a single polarization element, by using one port reflection amplifier is presented. 2 × subarray of the was implemented patch antennas, integrated with amplifiers fabricated in CMOS technology. In addition, 100 GHz active for transmitarray antenna also designed and fabricated, two-port high-gain phase rotator. Design principles integration process are Both antennas can be used either phased array or spatial modulation applications, as presented this paper....

A 240 GHz fundamental oscillator is demonstrated using the IBM CMOS SOI 32 nm process. The design was based on a Colpitts differential topology, where gate capacitance of device used as part inductor-capacitor tank for tuning. peak output power level 0.2 mW (-7 dBm) achieved, while total consumption 13 mW, reaching record efficiency 1.5 %. tuning bandwidth 11 achieved by changing bias level, range 13.5 controlling both and drain bias. consumes core area only 50×80 μm <sup...

A new topology of a reflection amplifier is proposed and demonstrated using CMOS FD-SOI 28 nm process for high gain reflectarray antenna applications. The design based on two sets cross coupled pairs which are inductively. An internal oscillations-block was implemented in order to improve the stability amplifier. Variable stable 5-25 dB at bandwidth 106-127 GHz achieved, with output power up 0 dBm (measurement limited). total consumption 6-20 mW, depending exact bias configuration. results...

A D-band low noise amplifier (LNA) has been fabricated in a 22 nm FD-SOI CMOS process for phased array radar applications. The LNA is composed of three identical stages neutralized common source topology. peak gain 21 dB was measured with input and output matching (S11 S22) better than −10 over the 131-162 GHz band. power consumption 28 mW expected figure (NF) 6-6.5 P1dB 3.8 dBm back-gate voltage 0 V. Increasing bias transistors to 1 V slightly increases improves NF, but also allows...

A new, low form factor topology of a phase rotator at 100 GHz is demonstrated using CMOS 65 nm process. The design based on two inductively coupled amplifiers, instead the common implementation with hybrid coupler. integrated multiple stage amplifiers in order to achieve high gain element for transmit/receive phased array antennas. full rotation peak 20-25 dB was achieved, total power consumption 90 mW. In addition, 2×2 active lens-array printed antenna designed and implemented, fabricated...