A5101513939- Low-power high-performance VLSI design
- Parallel Computing and Optimization Techniques
- Cloud Computing and Resource Management
- Software-Defined Networks and 5G
- Semiconductor materials and devices
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Caching and Content Delivery
- IoT and Edge/Fog Computing
- Advanced Memory and Neural Computing
- VLSI and FPGA Design Techniques
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Scottish History and National Identity
- Radiation Effects in Electronics
- Auction Theory and Applications
- Advancements in PLL and VCO Technologies
- Smart Parking Systems Research
- Cultural and Social Studies in Latin America
- Wireless Communication Networks Research
- Latin American Literature Studies
- Supply Chain and Inventory Management
- Distributed and Parallel Computing Systems
- Interconnection Networks and Systems
- Literacy and Educational Practices
California State University, Dominguez Hills
2020-2024
IBM (United States)
2006-2021
The 12-core 649mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors 31.5μF deep-trench decoupling capacitance. Three thin-oxide transistor V <inf xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> s are used for power/performance...
POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput supported 7.6 Tb/s of off-chip I/O bandwidth which provided three primary interfaces, including two new variants Elastic Interface as well embedded PCI Gen-3. Power efficiency improved several techniques. An on-chip controller based on an PowerPC™ 405 applies per-core DVFS adjusting DPLLs...
Cognitive computing and cloud infrastructure require flexible, connectable, scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, accelerator to address this need. The 24-core scale-out processor is implemented in 14nm SOI FinFET technology [1] contains 8.0B transistors. 695mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The IBM POWER7+™ microprocessor is the next-generation POWER® processor implemented in IBM's 32-nm silicon-on-insulator process. In addition to enhancing chip functionality, implementing core-level and chiplet-level power gating significantly increasing size of on-chip cache, achieves a frequency boost 15% 25% compared with its predecessor at same power. To achieve these challenging goals deliver serviceable power-frequency limited yield (PFLY), team made significant innovations post-silicon...
Meeting the power budget of 8 four-way simultaneous multithreading core IBM POWER7® microprocessor without compromising aggressive performance targets presented a considerable challenge to design team. Major innovations in modeling and reduction methodologies have been introduced at all levels design, including microarchitecture, logic, circuits, postlayout tuning, technology optimizations. In order use effectively resources available for reduction, team needed understand precisely where was...
POWER8™ delivers a data-optimized design suited for analytics, cognitive workloads, and today's exploding data sizes. The point results in 2.5x performance gain over its predecessor, POWER7+™, many workloads. In addition, POWER8 the efficiency demanded by cloud computing models also represents first step toward creating an open ecosystem server innovation.
The IBM POWER8™ processor is a 649-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">$^{2} $</tex-math></inline-formula> , 4.2-billion transistor, high-frequency microprocessor fabricated in the 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth...
The POWER9TM family of chips is fabricated in 14-nm silicon-on-insulator finFET technology using 17 levels copper interconnect. 695-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 24-core microprocessor features a new core based on an execution slice microarchitecture. chip contains 8 billion transistors and has 120 MB eDRAM L3 cache. processor adaptive clock strategy to reduce timing margin needed during power supply droop events by...
We introduce a generalized, efficient, and accurate power abstraction model generation techniques for complex IP blocks. This is based on the contributor modeling concept, which exploits nature of consuming components in design being inherently separable. The generated Process, Voltage Temperature (PVT) independent, thus enabling very efficient hierarchical analysis. Our approach constitutes industry's first methodology to automatically generate PVT independent abstracts. also describe...
We introduce a generalized, efficient, and accurate power abstraction model generation techniques for complex IP blocks. This is based on the contributor modeling concept, which exploits nature of consuming components in design being inherently separable. The generated Process, Voltage Temperature (PVT) independent, thus enabling very efficient hierarchical analysis. Our approach constitutes industry's first methodology to automatically generate PVT independent abstracts. also describe...
Virtual machine (VM) replication is an effective technique in cloud data centers to achieve fault-tolerance, load-balance, and quick-responsiveness user requests. In this paper we study a new fault-tolerant VM placement problem referred as FT-VMP. Given that different has fault-tolerance requirement (i.e., difference requires number of replica copies) compatibility some VMs their replicas cannot be placed into physical machines (PMs) due software or platform incompatibility), FT-VMP studies...
We present the novel micro-architectural features, supported by an innovative and pre-silicon methodology in design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) up to 3x socket level. In addition, a new feature supporting inline AI acceleration was added POWER ISA incorporated into POWER10 processor design. SIMD/AI performance be 10x for FP32 21x INT8 models ResNet-50 BERT-Large. this paper, we describe deployed used not only...
The continued scaling of gate oxide thickness in CMOS transistors has made dielectric integrity paramount to system functionality at low voltages. In this paper, the effect breakdown on minimum operating voltage (Vdd <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) a six transistor SRAM cell been examined. A new reliability model was developed explain non-monotonic operational shifts through product stress. Through simulation it...
Summary form only given, as follows. The end of transistor scaling drives innovative 2.5D, 3D and chiplet technologies to further extend Moore's law. Recent advancements in multi-die integration effectively reduce the costs at advanced nodes while providing more flexibility, modularity heterogeneous integration, which require designers rethink system architectures exploit these advantages. This forum focuses on most recent well key components for enable new architectures. aims bring together...
As compute power is increasingly migrated to large data centers and the cloud, microprocessors face progressively more stringent design constraints. This year's processor session introduces 5 new processors providing increased performance efficiency. In addition growing core counts, cache size, thread count, historical theme of integration continues as voltage regulators are now being implemented on chip. Other papers in this demonstrate creative self-monitoring adaptive techniques meet goals.
Prize-Collecting Traveling Salesman Problem (PC-TSP) is a new variation of TSP and defined as follows. Given weighted complete graph <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$G(V, E)$</tex> where node xmlns:xlink="http://www.w3.org/1999/xlink">$i\in V$</tex> has an available prize xmlns:xlink="http://www.w3.org/1999/xlink">$p_{i}$</tex> , two nodes xmlns:xlink="http://www.w3.org/1999/xlink">$s, t\in the goal traveling salesman to find...