A5026937849- VLSI and FPGA Design Techniques
- Time Series Analysis and Forecasting
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Low-power high-performance VLSI design
- Interconnection Networks and Systems
- 3D IC and TSV technologies
- GNSS positioning and interference
- Formal Methods in Verification
- Multimedia Communication and Technology
- Traffic Prediction and Management Techniques
- Machine Learning and Algorithms
- Advanced Optical Network Technologies
- Advancements in Photolithography Techniques
- Network Traffic and Congestion Control
- Adversarial Robustness in Machine Learning
- Integrated Circuits and Semiconductor Failure Analysis
- Manufacturing Process and Optimization
- Parallel Computing and Optimization Techniques
- Music and Audio Processing
- Physical Unclonable Functions (PUFs) and Hardware Security
Chinese University of Hong Kong
2022-2025
Shandong University of Science and Technology
2025
Hebei Agricultural University
2025
Face-to-face (F2F) stacked 3D IC is a promising alternative for scaling beyond Moore’s Law. In F2F ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource competition among all the nets due to constrained terminal number. advanced technology nodes, traditional planning may also introduce legality challenges of terminals, as metal pitches be much smaller than sizes terminals. Previous works attempt insert...
Accurately predicting satellite clock deviation is crucial for improving real-time location accuracy in a GPS navigation system. Therefore, to ensure high levels of positioning accuracy, it essential address the challenge enhancing prediction when high-precision data unavailable. Given frequency, sensitivity, and variability space-borne atomic clocks, important consider periodic variations bias (SCB) addition inherent properties clocks such as frequency deviation, drift, drift rate improve...
Face-to-face (F2F) stacked 3D IC is a promising alternative for scaling beyond Moore's Law. In F2F ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource competition among all the nets due to constrained terminal number. advanced technology nodes, such integration may also introduce legality challenges of terminals, as metal pitches be much smaller than sizes terminals. Previous works attempt insert...
Timing closure is crucial across the circuit design flow. Since obtaining sign-off performance needs a time-consuming routing flow, all previous early-stage timing optimization works only focus on improving early metrics, e.g., rough estimation using linear RC model or pre-routing path-length. However, there no consistency guarantee between metrics and performance. To enable explicit we propose novel framework, TSteiner. This paper demonstrates ability of learning framework to perform robust...
Arithmetic block identification in gate-level netlists plays an essential role for various purposes, including malicious logic detection, functional verification, or macro-block optimization. However, current methods usually suffer from either low performance poor scalability. To address the issue, we come up with a novel framework based on graph learning and network flow analysis, that extracts desired components complete circuit netlist. We design asynchronous bidirectional neural (ABGNN)...