A5053598579- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques
- Ferroelectric and Negative Capacitance Devices
- Network Traffic and Congestion Control
- Experimental Learning in Engineering
- Network Packet Processing and Optimization
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Embedded Systems Design Techniques
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Software Testing and Debugging Techniques
- Smart Grid and Power Systems
- Open Source Software Innovations
- Matrix Theory and Algorithms
- Advanced Optical Network Technologies
- Advanced Graph Neural Networks
- Text and Document Classification Technologies
- Machine Learning and Algorithms
- Neural Networks and Applications
- Model Reduction and Neural Networks
- Particle Detector Development and Performance
- Distributed and Parallel Computing Systems
Chinese University of Hong Kong
2025
Southeast University
2022-2024
Beijing Normal University
2024
With diminishing margins in advanced technology nodes, the performance of static timing analysis (STA) is a serious concern, including accuracy and runtime. The STA can generally be divided into graph-based (GBA) path-based (PBA). For GBA, results are always pessimistic, leading to overdesign during design optimization. PBA, pessimism reduced via propagating real path-specific slews with cost severe runtime overheads relative GBA. In this work, we present fast accurate predictor post-layout...
Accurate wire timing estimation has become a bottleneck in optimization since it needs long turn-around time using sign-off timer. The gate can be calculated accurately lookup tables cell libraries. In comparison, the accuracy and efficiency of calculation for complex RC nets are extremely hard to trade-off. limited number paths opens door graph learning method estimation. this work, we present fast accurate estimator based on novel architecture, namely GNNTrans. It generate path...
With transistors scaling down, aging effects become increasingly significant in circuit design. Thus, the aging-aware cell timing model is necessary for evaluating aging-induced delay degradation and their impact on performance. However, tradeoff between accuracy efficiency becomes a bottleneck traditional methods. In this brief, we propose fast accurate via graph learning. The information of multi-typed devices different arcs can be embedded by heterogeneous attention networks (H-GAT)...
In advanced technology nodes, aging effects like negative and positive bias temperature instability (NBTI PBTI) become increasingly significant, making timing closure optimization more challenging. Unfortunately, conventional critical path (CP) selection tools used in reliability-aware design flow cannot accurately identify CPs under different conditions. To address this issue, we propose an aging-aware CP comprising two parts: 1) cell detection 2) criticality (PC) computation. We employ...
As the transistor technology nodes shrink into nano-scales, timing guardbands caused by aging effects and process variations continue to increase. Approximate computing can eliminate aging-and-variation-induced without sacrificing design performance. It apply local approximate changes (LACs) automatically in circuits reduce critical path delay. However, efficiently achieving optimization under error distance constraints is still tricky. This work proposes an automated timing-driven mapping...
Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate works cannot optimize on multiple paths simultaneously and neglect the constraint layouts. They cause sub-optimal solutions low-efficiency issues when compared with commercial tools. In this work, we propose a learning-driven physically-aware framework to performance large-scale circuits efficiently. our gradient descent optimization-based for obtaining accurate gradients,...
The advanced multi-core technology enables parallel computing to speed up Automatic Test Pattern Generation (ATPG). main challenge is solve an increasing number of hard-to-solve faults effectively. In this paper, we develop efficient system for the ATPG program, i.e., FPGNN-ATPG, which consisted two parts: graph-neural-networks-based (GNN-based) fault classification and fault-driven deterministic test pattern generator (DTPG). end-to-end GNN-based classifier can predict types with superior...
Time Constant Equilibration Reduction (TICER) is a famous RC reduction method. Traditional TICER performs the floating-point operations repeatedly in time constants calculation, which time-consuming to deal with large-scale interconnect. This paper converts node elimination speed-up problem into classification issue by abstracting network as graph structure. The deep anomaly detection method adopted address data imbalance among nodes. proposed GNN-based validated on benchmark circuits size...