To improve the precision of keyword spotting (KWS) for individual users on edge devices, we propose an on-chip-training KWS (OCT-KWS) chip private data protection while also achieving ultralow -power inference. Our main contributions are: 1) identity interchange and interleaved pipeline methods during backpropagation (BP), enabling pipelined execution operations that traditionally had to be performed sequentially, reducing cache requirements loss values by 95.8%; 2) all-digital...

Placement is crucial in physical design flow with significant impact on later routability and ultimate manufacturability terms of performance, power, area (PPA), which may deviate from finding the optimal solution and/or lead to unnecessary iterations suffering interleaved optimization steps inaccurate PPA estimation. To solve this issue, we propose a physical- timing-related placement guidance framework provides candidate gate sizing buffer insertion solutions as well path group for...

A coarse-grained reconfigurable processing unit (RPU) consisting of 16 ×16 multi-functional elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a 5.4 mm ×3.1 die in TSMC 65 nm LP1P8M CMOS technology. hierarchical configuration context (HCC) organization scheme proposed to reduce the implementation overhead and energy dissipation spent fast reconfiguration. The RPU integrated into two system-on-a-chips (SoCs), targeting...

Timing estimation prior to routing is of vital importance for optimization at placement stage and timing closure. Existing wire- or net-oriented learning-based methods limits the accuracy efficiency prediction due neglect delay correlation along path computational complexity accumulation. In this paper, an efficient accurate pre-routing framework proposed by employing transformer network residual model, where physical information extracted as sequence features while modeled calibrate...

In this paper, we introduce a coarse-grained dynamically reconfigurable fabric, named Reconfigurable Processing Unit (RPU), which is implemented on 5.4×3.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon with TSMC 65 nm LP1P8M technology. This fabric consists of 16×16 multi-functional Elements (PEs) interconnected by an area-efficient Line-Switched Mesh Connect (LSMC) routing. A Hierarchical Configuration Context (HCC)...

The coarse-grained reconfigurable architecture (CGRA) is proven to be energy efficient in several specific domains. In CGRAs, the on-chip memory hierarchy, which contains context and data organizations, should well considered achieve appropriate tradeoffs among three aspects: 1) performance; 2) area; 3) power. this paper, two techniques called hierarchical configuration (HCC) lifetime-based data-memory organization (LDO) focusing on organizations are proposed compress space reduce...

This paper proposes a novel sub-architecture to optimize the data flow of REMUS-II (REconfigurable MUltimedia System 2), dynamically coarse grain reconfigurable architecture. consists µPU (Micro-Processor Unit) and two RPUs (Reconfigurable Processor Unit), which are used speeds up control-intensive tasks data-intensive respectively. The parallel computing capability flexibility makes itself an excellent candidate process multimedia applications, require large amount memory accesses. In this...

Voltage scaling technique is widely employed in state-of-the-art low power circuits with excellent reduction. However, voltage to sub-threshold (STV) and near-threshold (NTV) domain introduces performance degradation high process variation sensitivity. Accurate modeling of the statistical characteristics especially probability distribution function (PDF) cumulative (CDF) urgently required consideration. In this paper, a novel analytical model derived based on log-skew-normal (LSN) precisely...

Differential power analyses (DPA) have become great threats to cryptographic chips. However, the DPA resistance evaluation is difficult during circuit design time. In this paper, a simulation test platform at time and an experimental measurement are built evaluate resistant capability of The security obtained by dynamic taking timing behavior into account, which uses time-based mode PrimeTime Power Extension (PTPX) accurate characterization. effects both platforms verified on unprotected...

This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development wearable applications, power consumption has become one primary challenges for IC designs. To improve efficiency, prefer scheme is to operate at an ultra Near Threshold Voltage (NTV). For performance variation degradation, self-adaptive margin assignment technique proposed in...

Critical path generation poses significant challenge to integrated circuit (IC) design flow in terms of huge computational complexity and crucial impact optimization, whose early prediction is vital importance for accelerating the closure, especially under multiple process-voltage-temperature (PVT) corners. In this work, a post-routing critical framework proposed based on Bidirectional Long Short-Term Memory (BiLSTM) network Multi-Layer Perceptron (MLP) learn from sequential features global...

Timing mismatch between different stages of physical design poses great challenges for circuit optimization to achieve the desired performance, power, and area (PPA) tradeoff. The inaccurate timing estimation prior routing may lead over-design with unwanted power consumption or iterating back cell placement at cost turn-around time. Existing learning models could not predict post-routing satisfying accuracy efficiency due limitations ignorance delay correlation along path empirical feature...

This paper presents a novel architecture design to optimize the reconfiguration process of coarse-grained reconfigurable (CGRA) called Reconfigurable Multimedia System II (REMUS-II). In REMUS-II, tasks in multi-media applications are divided into two parts: computing-intensive and control-intensive tasks. Two Processor Units (RPUs) for accelerating Micro-Processor Unit (µPU) contained REMUS-II. As large-scale CGRA, REMUS-II can provide satisfying solutions terms both efficiency flexibility....

Combined experimental and numerical studies are conducted to study ice storage performance of an tank with finned tube. Axially arranged fins on the refrigerant tube applied enhance solidification. The evolution solid–liquid interface variation temperature typical position is examined. effect natural convection discussed in detail. In addition, effects initial water analyzed. results indicate that enhanced by metal remarkably. defection poor heat transfer after formed can be solved applying...

Laser cladding is mainly applied in components renovation, coating, stacking forming, etc.At present, the degree of automation laser not very high.Machine vision technology gradually becoming a good approach to improve automaticity.Utilizing machine measure and control molten pool has become an important research interest.Clear image was acquired with appropriate grabbing installation system together processing methods, area calculated.Analyzed variation as parameters changed.Discussed...

This paper presents a configuration compression approach for coarse-grain reconfigurable architectures (CGRA) to reduce the context size in caches, and therefore improve reconfiguration efficiency of CGRAs. Firstly, some kernel sub-algorithms radar signal processing including FFT, FIR Matrix Inversion are analyzed, explore features that contexts consist repetition same blocks Then, is proposed redundancies when they loaded into cache. The experimental results show can drastically context,...

Wide voltage design provides the tremendous benefits for state-of-the-art circuit in terms of power consumption reduction and energy efficiency enhancement. The traditional verification flow depends on standard cell libraries, which are only available from foundries limited PVT (Process-Voltage-Temperature) corners near nominal voltages, leading to remarkable characterization effort storage overhead. In this paper, a learning-based framework is proposed predict path delays across multiple...