A5069497008- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Semiconductor Lasers and Optical Devices
- Advancements in PLL and VCO Technologies
- Radiation Detection and Scintillator Technologies
- Photonic and Optical Devices
- Particle physics theoretical and experimental studies
- Electromagnetic Compatibility and Noise Suppression
- Medical Imaging Techniques and Applications
- Radio Frequency Integrated Circuit Design
- Dark Matter and Cosmic Phenomena
- Neutrino Physics Research
- Advanced Semiconductor Detectors and Materials
- 3D IC and TSV technologies
- Advanced Optical Sensing Technologies
- Analog and Mixed-Signal Circuit Design
- Blind Source Separation Techniques
- Neural Networks and Applications
- Nuclear Physics and Applications
- Atomic and Subatomic Physics Research
- Electron and X-Ray Spectroscopy Techniques
- Advanced X-ray and CT Imaging
- Radiomics and Machine Learning in Medical Imaging
- High-Energy Particle Collisions Research
- Eosinophilic Disorders and Syndromes
Central China Normal University
2019-2024
Timing systems based on Analog-to-Digital Converters are widely used in the design of previous high energy physics detectors. In this paper, we propose a new method deep learning to extract time information from finite set ADC samples. Firstly, quantitative analysis traditional curve fitting regarding three kinds variations (long-term drift, short-term change and random noise) is presented with simulation illustrations. Next, comparative study between neural networks made demonstrate...
Abstract This paper presents the design and test results of a 25 Gbps VCSEL driving ASIC fabricated in 55 nm CMOS technology as an attempt for future very high-speed optical links. The is composed input equalizer stage, pre-driver stage novel output driver stage. To achieve high bandwidth, combines inductor-shared peaking structure active-feedback technique. A uses pseudo differential CML adjustable FFE pre-emphasis technique to improve bandwidth. has been integrated customized module with...
Electrical characterization data are presented in this paper to demonstrate a low cost, mid-I/O range plastic ball grid array (PBGA) package as an effective packaging solution for 10 Gb/s applications such SONET/SDH and Ethernet.
Abstract This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is single-channel bidirectional (1Tx + 1Rx) ASIC, including Laser Driver (LD) module Limiting Amplifier (LA) module. It would drive Vertical Cavity Surface Emitting (VCSEL) Transmitter Optical Sub-Assembly (TOSA) receive signals from Photo Diode (PD) Receiver (ROSA), respectively. In LDLA14, novel...
Abstract The Topmetal detector, utilized in this investigation, is a direct-type CMOS pixel sensor known for its distinctive feature of employing exposed metal at the top each to directly capture external charged particles. This method generates electrical signals through induction charge. At present, it mainly used gas detector(GPD) and particle beam monitoring. In paper, we present new front-end design aimed enhancing capabilities detector. focus on incorporating Time-Digital Conversion...
Abstract This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The would be used downlink data transmission MPD readout system to recover serial from back-end parallel front-end. adopts tree-type structure, consisting high-speed receiver (RXDATA), clock (RXCLK), four levels demultiplexer (DEMUX) modules, dividers 16 Low-Voltage Differential...
Abstract This paper presents the design and test results of a 14 Gbps VCSEL driving ASIC with novel output driver structure fabricated in 55 nm CMOS process. It consists an equalizer stage, limiting amplifier stage stage. The uses CTLE to compensate high frequency losses at PCB traces, bonding wires input pads. To meet both gain/bandwidth requirements area restriction, adopts inductor-shared peaking technology. increase voltage headroom improve bandwidth, using on-chip AC coupling, stacked...
Abstract This paper presents the design and test results of a low noise PLL ASIC for optical data transmission system in NICA MPD project. In proposed PLL, novel charge pump circuit uses two feedback operational amplifiers to obtain leakage current reduce dynamic mismatch. A LC-VCO combines two-step capacitor tuning structure array unit reasonable frequency range an optimized Q factor performance. The has been fabricated 55 nm CMOS process. show that outputs 5.12 GHz clock with phase −108...
This paper describes comprehensive electrical design and characterization of differential pairs in low cost high frequency/speed electronic packages. A general methodology has been applied to pair several PBGA packages developed for 10 Ghps applications. The generalized mixed-mode S-parameter theory used the is presented along with a comparison broadband simulated models extracted empirical circuit models. These are transient analysis show performance improvement signaling over single-ended...