A5087116772- Interconnection Networks and Systems
- Low-power high-performance VLSI design
- COVID-19 Digital Contact Tracing
- Advancements in Semiconductor Devices and Circuit Design
- Privacy-Preserving Technologies in Data
- Advanced Memory and Neural Computing
- Data-Driven Disease Surveillance
- Parallel Computing and Optimization Techniques
- Analog and Mixed-Signal Circuit Design
- Radiation Effects in Electronics
- Quantum-Dot Cellular Automata
- Embedded Systems Design Techniques
- VLSI and FPGA Design Techniques
- Supercapacitor Materials and Fabrication
- Distributed systems and fault tolerance
National Institute of Technology Srinagar
2017-2023
Lovely Professional University
2014
University of Kashmir
2014
Contact Tracing is considered as the first and most effective step towards containing an outbreak, resources for mass testing large quantity of vaccines are highly unlikely available immediate utilisation. Effective contact tracing can allow societies to reopen from lock-down even before availability vaccines. The objective mobile speed up manual interview based process outbreak efficiently quickly. In this article, we throw light on some issues challenges pertaining adoption solutions...
This paper present a comparison between the design of 8T adder based Carry Select Adder (CSA) and 10T CSA. Using both designs adders 4-bit CSA architecture has been developed compared with 28T The reduced delay, power area as slight tradeoff for to analysis shows that is better than work evaluates performance in terms power, delay using 180nm CMOS process technology Cadence Virtuoso tool Spectre simulator.
In order to meet the need for high-speed data processing, system designers have adopted Multi-Processor System-on-Chip (MPSoC) design. Network-on-chip (NoC) promises be a viable solution as basic communication fabric such designs. A router is component of NoC and using efficient internal blocks design expected improve performance whole. One block prime importance an arbitration unit. The commonly used logics include Fixed Priority, Lottery Round Robin algorithm. However, they lack capability...
An arbiter is identified as one of the critical components NoC router.Among various arbitration schemes, Round-Robin among popular schemes.In this work we have proposed an scheme that will be able to solve problem constant wait time a conventional and provided some additional features well.The superiority design its ability overcome time, by identifying real-time requirements each port, based on information from respective buffers.The feature algorithm fault-tolerant behavior for errors...
Purpose This work focused on a basic building block of an allocation unit that carries out the critical job deciding between conflicting requests, i.e. arbiter unit. The purpose this is to implement improved hybrid while harnessing advantages matrix arbiter. Design/methodology/approach approach design methodology involves extraction traffic information from buffer signals each port. As arrives in respective ports, these buffers acts as source differentiation ports receiving low rates and...
This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) First Zero Finding (FZF) logic techniques with optimization Full (FA) cell by minimize number transistors. The results have been analyzed compared for both above styles 28T, 10T 8T FA cells where as keeping all other basic used FZF based CSA same three adder cells. analysis that is better in terms power consumption Power Delay Product (PDP) however proves to be transistors...