A5101710372- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Analog and Mixed-Signal Circuit Design
- Engineering Applied Research
- Semiconductor Lasers and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Acoustic Wave Phenomena Research
- Thermal Analysis in Power Transmission
- Semiconductor materials and devices
- Photonic and Optical Devices
- VLSI and Analog Circuit Testing
- Sensor Technology and Measurement Systems
- Advanced Fiber Laser Technologies
- High-Voltage Power Transmission Systems
- Industrial Engineering and Technologies
- Electric Power Systems and Control
- Korean Urban and Social Studies
- Aerosol Filtration and Electrostatic Precipitation
- Electrical Fault Detection and Protection
- Structural Health Monitoring Techniques
- Electromagnetic Fields and Biological Effects
- Engineering and Technology Innovations
- Advancements in Semiconductor Devices and Circuit Design
- Vibration and Dynamic Analysis
- Advanced Measurement and Metrology Techniques
Korea Advanced Institute of Science and Technology
2015-2025
Samsung (South Korea)
2018-2025
Harvard University
2024
Korea Institute of Brain Science
2024
Electric Power Research Institute
2006
Korea Electric Power Corporation (South Korea)
2001
To fully understand how the human brain works, knowledge of its structure at high resolution is needed. Presented here a computationally intensive reconstruction ultrastructure cubic millimeter temporal cortex that was surgically removed to gain access an underlying epileptic focus. It contains about 57,000 cells, 230 millimeters blood vessels, and 150 million synapses comprises 1.4 petabytes. Our analysis showed glia outnumber neurons 2:1, oligodendrocytes were most common cell, deep layer...
Abstract As Moore’s law approaches its physical limits, the semiconductor industry has begun to focus on improving I/O density and power efficiency through 2.5D/3D packaging. Heterogeneous integration, which combines integrated circuit blocks from different linewidth processes into a single package, is central these developments. To ensure stable connections with high yield in back-end processes, precision speed 3D surface measurement prerequisite. Existing methods such as white-light...
This paper presents a reference-less digital clock and data recovery (CDR) for liquid crystal display (LCD) intra-panel interfaces. The increments of the resolution, color depth, frame rate demand high speed transmission capacity between timing controller source driver IC (SDIC). As increases, performances CDR in SDIC especially tolerance input jitter ground noise become important to recover without an error. work exploits half-bit previous with feed forward method early/late signal from be...
In this brief, a 0.9-V 12-Gb/s quarter-rate two finite impulse response tap direct decision feedback equalizer (DFE) is presented. For high-speed incorporated operation of both DFE summing and slicing, common-mode-controlled charge-based latch (CMCCBL) proposed. CMCCBL-based DFE, the common mode first signal changed to adjust weight. Therefore, CMCCBL does not need conventional weighting transistors which increase delay. The core compensates for FR4 printed circuit board channel loss −22 dB...
This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock (LD) can detect not only the frequency difference between VCO and target but also coarse position. With help of LD, RICPD has simple architecture using AND gates, relieving mismatches in PD charge pump. Additionally, improves performance noise by ripple compensation technique solves...
This paper describes a novel integrated time register and arithmetic circuit (TRAC) for time-domain signal processing (TDSP). TRAC has four basic functions: register, adder, subtractor, amplifier. One is able to accept multiple inputs perform the combination of functions. Thus, complex operations can be performed synchronously with TRAC. In synchronous time-to-digital converter (TDC), high-gain residue amplifier suppressed offset-time component at output implemented by exploiting advantages...
This brief presents a quarter-rate 1 finite impulse response and infinite (IIR) direct decision feedback equalizer (DFE). The proposed non-time-overlapping data generation enables the elimination of all two-stacked clocked transistors in 4:1 current-mode-logic multiplexer conventional IIR DFEs. Therefore, delay is improved without static current this brief. Fabricated 65-nm CMOS, DFE achieves power efficiency 0.43 pJ/b at rate 10.8 Gb/s 1-V supply. A BER < 10 <sup...
This paper presents a 2 GHz injection-locked PLL (ILPLL) with an frequency divider (ILFD). Using negative phase shift phenomenon of the ILFD, injection timing can be calibrated without delay line. As result, proposed ILPLL achieves simple background calibration for robustness power supply variation. The test core has been fabricated in 65nm CMOS process consuming 3.74mW at 0.9V voltage.
This brief presents a 0.65-V power noise tolerant source-synchronous injection-locked receiver with 13.4 dB channel loss compensation. To meet the 1UI timing constraint for decision feedback equalizer in low supply, SR latches are removed path and return to zero recovered data is used equalization. Additionally, sensitivity of supply relieved by current pMOS body bias control techniques an oscillator. The test core fabricated 65-nm CMOS process achieves 11.2 Gb/s 0.303 pJ/bit FOM...
This brief presents an input-data-jitter-tolerant injection-type clock and data recovery (CDR) circuit with a super-harmonic injection-locked ring oscillator (SH-ILRO). Unlike prior CDRs that utilize power-hungry CML-type injection path or for which the rate is limited to process-defined CMOS logic bandwidth, proposed CDR achieves energy-efficient edge injection. The wide-bandwidth source follower-based detector extracts input energy efficiently. SH-ILRO enables quarter-rate...
This brief presents a reference-less baud-rate digital clock and data recovery (CDR) with decision feedback (DDF) direct method (DFM). The DDF DFM has been used for the equalization of channel loss serial link equalizer. However, we apply to CDR reduce number samplers, which is dropped 2/3 compared conventional CDR. As result, power consumption mismatch problem samplers can be reduced. test chip fabricated in 65-nm CMOS technology operates at 10-Gb/s rate 13.84-mW consumption.
The large increase in the use of electricity has resulted an ever-growing electric power demand. It created need for construction transmission facility located close to load centers and it also require wide right-of-way lots, that are not always available, especially installation towers. difficulties acquiring have put pressure on energy companies either upgrade a line existing higher voltage or build new narrow right-of-way. This paper presents design compact tower with polymer Insulation...
In this work, prior measurements have been carried out of the human exposure to magnetic field near power facilities in Korea according measurement procedures IEC PT62110. These aim for evaluating levels by use newly proposed PT62110 body fields on general public. For purpose, statistical treatment has conducted with measured data uniform and non-uniform exposure.
This paper presents a clock-path feedback equalization receiver with unfixed tap weighting property. In the proposed receiver, an operation is achieved through clock path so that loop delay improved. Moreover, weight changeable depending on amount of inter-symbol interference (ISI) resulting in single compensates high channel loss. Fabricated 65 nm CMOS, achieves power efficiency 0.376 mW/Gbps at data rate 12.5 Gb/s 0.87 V supply. A BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
본 논문에서는 산불이 송전용 폴리머애자에 미치는 영향을 연구하기 위해 인공화염 시험장치를 제작하여 화염의 가열 시간에 따른 폴리머애자의 갓(shed) 변화와 자기애자의 disc 변화를 관찰하고, 전기적?기계적 실험을 통하여 특성변화를 확인하였다. 실험결과 다음과 같은 결론을 얻을 수 있었다. 첫째, 가열시간이 5분정도 경과하였을 때, 전기적 특성은 80[%] 정도 저하된 반면에 경우 갓 유실이 있었지만 특성의 변화는 10[%] 정도였다. 폴리머애자를 20분 가열하였을 때는 대부분의 갓이 유실되었지만 특성치는 20[%]정도 감소하였다. 둘째, 폴리머애자와 자기애자 모두 특성치의 감소는 기계적 양호하게 나타났다.
K. Tanabe and Miyajima comment on the paper by K.-H. Yang et al. (see ibid., vol.15, no.4, p.1243-51, 2000) ask three questions of authors. The original authors reply to comments.