A5040282260- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Analog and Mixed-Signal Circuit Design
- Low-power high-performance VLSI design
- Analytical Chemistry and Sensors
- Sensor Technology and Measurement Systems
Samsung (South Korea)
2022-2025
Yonsei University
2022-2023
This article presents a process, voltage, and temperature (PVT)-robust capacitively degenerated dynamic amplifier as the residue of low-power pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed achieves voltage gain 16 with two-stage configuration high linearity over wide range an on-chip timing generator. work solves problems related to low temperature–sensitivity amplifier, while retaining advantages linearity, output swing, energy efficiency....
This paper presents a capacitively degenerated two-stage dynamic amplifier that achieves high voltage gain and good linearity in residue of pipelined SAR ADC. It uses an open-loop exploits capacitive degeneration, its limited is improved to 16× by using configuration. Since the optimal timing achieve can be set with simple generator, error due incomplete settling maintained negligible power overhead. Fabricated 65-nm CMOS process, ADC 65-dB SNDR 79.8-dB SFDR at sampling rate 50 MS/s, while...
Pipelined SAR ADCs are widely used for moderate-to-high resolution applications. In this architecture, a residue amplifier plays key role in speed and linearity, so it is inevitable that the consumes large amount of power to achieve target performance. Several topologies such as Gm-based amplifier, ring floating inverter (FIA) [1]–[3] have been developed improve energy efficiency represent successful alternative conventional OTAs. However, achieving high bandwidth while maintaining good...