A5081601806- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Photonic and Optical Devices
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Blind Source Separation Techniques
- VLSI and Analog Circuit Testing
- CCD and CMOS Imaging Sensors
- Semiconductor Lasers and Optical Devices
- Radio Frequency Integrated Circuit Design
- Sparse and Compressive Sensing Techniques
- Full-Duplex Wireless Communications
- X-ray Spectroscopy and Fluorescence Analysis
- Low-power high-performance VLSI design
- Sulfur Compounds in Biology
- Electron and X-Ray Spectroscopy Techniques
- Face and Expression Recognition
- Advanced Photonic Communication Systems
- Analytical Chemistry and Sensors
- Optical Network Technologies
- Advanced Adaptive Filtering Techniques
- Face recognition and analysis
- Cleft Lip and Palate Research
- Facial Rejuvenation and Surgery Techniques
- Advancements in Photolithography Techniques
Samsung (South Korea)
2011-2025
Gwangju Institute of Science and Technology
2019-2022
National Radio Research Agency
2022
Massachusetts Institute of Technology
2019
Pohang University of Science and Technology
2000-2012
An all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its resolution according to input time difference. By cascading 2× amplifiers, the efficiently generates exponent-only information fractional To improve linearity in wide range, replica-based self-calibration scheme applied amplifier. The TDC, implemented 0.18 μm CMOS, shows minimum of 1.25 ps total conversion range 2.5 ns, maximum operating frequency 250 MHz, and power consumption 1.8 mW...
This paper describes the first implementation of well-known cyclic ADC architecture into a time-to-digital converter. With an asynchronous clocking scheme, all-digital 1.5b time-domain multiplying DAC (MDAC) is repetitively used for 8b conversion. The MDAC based on 2 × time amplifier with offset-compensated gain calibration scheme. proposed TDC, fabricated in 0.13 μm CMOS, shows resolution 1.25 ps total conversion range ±160 ps, maximum operating frequency 100 MHz, and power consumption 4.3...
This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An clocking scheme realizes operation for higher The TDC was standard 0.13-μm CMOS technology has maximum throughput of 300 MS/s resolution 1.76 ps total conversion range 1.8 ns....
The CDR circuit is a key enabling block in high-speed serial links. With an external reference clock for frequency acquisition, high-performance circuits typically operate at single pre-defined data rate. In rapidly growing telecommunication applications, however, it desirable to be able cover wide range of bit rates improved flexibility. the WDM technique, example, can transmitted with different rates. Thus, desired that detects change input rate and automatically acquire new without any...
This paper presents a low-power noise-shaping ΔΣ time-to-digital converter (TDC) and its application to fractional-N digital PLL. With simple structure of single-delay-stage Δ modulator followed by charge pump based Σ modulator, wide range TDC input is converted modulated single bit stream without loss signal information. The architecture effectively improves the conversion performance linearity resolution while handling large due operation dual-modulus divider. In addition, with downscaling...
The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb with a per-bit trainable single-ended decision feedback equalizer (DFE), reference impedance (ZQ)-coded transmitter, and phase-locked loop (PLL)-less clocking I/O speed by process. Furthermore, this optimizes clock- power-domain crossings adopts split-die architecture improve signal integrity (SI). operates 16 Gb/s/pin 1.15 V...
Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although GDDR5X can operate 12Gb/s [3] by increasing the burst length (BL) from 8 to 16, a degradation in system performance data granularity of 64B is seen. The I/O specification, using PLL clocking that additionally causes jitter, has not changed much compared GDDR5. To overcome these issues, GDDR6 introduced dual...
With the growth of wearable devices, such as smart watches and glasses, there is an increasing demand for lower power dissipation, to achieve longer battery life with limited capacity. Nevertheless, memory bandwidth needs increase support high-resolution graphic engines. Since most devices are event driven, they consume a bulk in standby mode. Therefore, it crictical reduce standby-mode power, well improve active-mode efficiency. However, DRAM's periodic self-refresh, critical data...
A new concept of floating-point-number representation is implemented in a time-to-digital converter (TDC), which adaptively scales its resolution according to the amount input difference. With fixed 6-bit significand number, TDC provides five cases exponent (x1, x2, x4, x8, and x16) indicate scale information. digital phase-locked loop (PLL) with 0.18-μm CMOS. The shows minimum 3 ps total conversion range 3.5 ns, maximum operating frequency 80 MHz, power consumption 18 mW at 75 MHz. PLL lock...
The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity proportional one-inverter delay [1]. For fine resolution, vernier chains are frequently used [2,3]. Since determined by difference between two inverter delays, a large number stages required cover detection range, resulting in long conversion and high power consumption. Well-established data-conversion architectures have also been sought achieve both range [4,5]....
In this article, a high-speed antenna measurement system using multi-probe array technique for 5G application is suggested. The spherical near-field scan millimeter wave frequency band (3 GHz–40 GHz) and the rotation method adopted to improve speed. proposed RF consists of 14 (28 channel with dual-polarization), switch matrix, downconverters, amplifiers/attenuators, digitizers, signal generators, compared conventional planar system. speed performance can be improved significantly 3D beam...
This brief presents a differentially terminated CML transmitter with self-calibration scheme based on time-domain reflectometry for preemphasis strength control. Without any handshaking or receiver mode control, the measures time of flight by applying same step input two transmission lines differential link. Since does not change its configuration, proposed greatly simplifies adaptation. To verify calibration scheme, is fabricated in 0.18 ¿m- CMOS. For various lengths microstrip line printed...
The replicated resist pattern characteristics caused by photoelectrons and Auger electrons generated from the W substrate were investigated for 100 nm proximity x-ray lithography. In addition, simulations a hard spectrum having 2.36 keV average energy performed to investigate electron effects in experiments, it was found that secondary undercut footing of profiles at resist–substrate interface. Several buffer layers with varying thicknesses tested reduce photoelectron substrate. best...
In compressed sensing (CS), quantization is essential for efficient discretization in real systems, but its large bit depth increases hardware complexity and energy consumption. To overcome these issues, 1-bit CS regarded as a new data acquisition technique. this paper, we discover that there exist optimum modulation orders orthogonal multicarrier transmission of signals over wireless channels. specific, develop an upper bound on the reconstruction errors when modulated are transmitted...
OFDM 기반 통신시스템에서 압축 센싱을 단계적으로 적용하여 임펄스 잡음과 클리핑 잡음을 제거하는 방법을 제안한다. 이 방법은 1단계로 적응적 임계값을 적용한 블랭킹 기법을, 2단계 및 3단계에서 센싱 기법을 반복적으로 적용하며 판정 궤환을 통해 비트 오율을 점차 감소시킨다. 잡음 채널에서 모의실험결과 오율이 <TEX>$10^{-5}$</TEX>일 때 4.5dB의 SNR 이득을 얻을 수 있었다. A compressive sensing based iterative scheme for reducing both the impulsive noise as well clipping is proposed OFDM-based communication systems. Nonlinear blanking using adaptive thresholds used in 1st stage followed by two consecutive detection with aid of decision...
In this paper, we propose a novel loss function for deep face recognition, called the additive orthant (Orthant loss), which can be combined softmax-based functions to improve feature-discriminative capability. The Orthant makes features away from origin using rescaled softplus and an margin. Additionally, compresses feature spaces by mapping of each class element-wise operation 1-bit quantization. As consequence, improves inter-class separabilty intra-class compactness. We empirically show...