A5046432008- VLSI and Analog Circuit Testing
- Advancements in Photolithography Techniques
- Nuclear and radioactivity studies
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Risk and Safety Analysis
- Combustion and Detonation Processes
- Interconnection Networks and Systems
- VLSI and FPGA Design Techniques
- Embedded Systems Design Techniques
- Wireless Sensor Networks for Data Analysis
- Industrial Vision Systems and Defect Detection
IBM (India)
2020-2022
IBM (United States)
2015
Kumaun University
2010
As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from shape and nearby blockages, becomes main cause for DRC violations. Therefore, machine learning model hotspot prediction needs to consider both very high-resolution patterns low-resolution layout information as input features. A new convolutional neural network technique, J-Net, introduced with mixed resolution This customized architecture that flexible handling...
This paper explores the possibility of providing traffic control signals through radio frequency (RF) transmission or by other means wireless data communication and thereby reduce road accidents. Additional advantages can be reducing car speed stopping at breakers, no entry zones police barricade. system if adopted some state effectively number accidents caused speeding vehicles Losing vehicle breakers driver's negligence towards signals. The primary model this consists a microcontroller...
Early design analysis is essential for better definition and efficient balancing of effort risk. In this paper, we introduce the concept virtual logic netlist (VLN), a potentially incomplete yet representative hierarchical logical graph design. VLN enables early rapid register transfer level (RTL) using accurate backend tool engines without need time-intensive synthesis techniques. We discuss creation VLN, its application to enable RTL clock gating analysis. Experimental evaluation performed...
As the semiconductor process technology advances into sub-10-nm regime, cell pin accessibility, which is a complex joint effect from shape and nearby blockages, becomes main cause for design rule violations (DRVs). Therefore, machine-learning model DRV prediction needs to consider both very high-resolution patterns low-resolution layout information as input features. A new convolutional neural network technique, J-Net, introduced with mixed resolution This customized architecture that...
Sub-7nm technology nodes have introduced new challenges, specifically in the lower metal layers. Extreme Ultraviolet Lithography (EUV) and multi-patterning-based lithography such as Self-Aligned Double Patterning (SADP) solutions become key choices for manufacturing of these The demand microprocessors has increased tremendously last few years this imposes another challenge to chip manufacturers build their products at a very rapid rate. These days mix different layers is quite common. We...