A5055944364- Advanced Memory and Neural Computing
- Neural Networks and Reservoir Computing
- Neuroscience and Neural Engineering
- Ferroelectric and Negative Capacitance Devices
- Physical Unclonable Functions (PUFs) and Hardware Security
- Optical Network Technologies
- CCD and CMOS Imaging Sensors
- Neural dynamics and brain function
- Neural Networks and Applications
- Phase-change materials and chalcogenides
- Transition Metal Oxide Nanomaterials
- Machine Learning and ELM
- Quantum-Dot Cellular Automata
- Neural Networks Stability and Synchronization
- Semiconductor materials and devices
- Software System Performance and Reliability
- Photoreceptor and optogenetics research
- Random lasers and scattering media
- Cognitive and developmental aspects of mathematical skills
- Wireless Signal Modulation Classification
- Low-power high-performance VLSI design
- AI-based Problem Solving and Planning
- Internet Traffic Analysis and Secure E-voting
- dental development and anomalies
- Education and Technology Integration
United States Air Force Research Laboratory
2015-2024
Guardant (United States)
2022
U.S. Air Force Research Laboratory Information Directorate
2010-2020
Western University of Health Sciences
2017
University at Albany, State University of New York
2012
UNSW Sydney
1970
Information security has emerged as an important system and application metric. Classical solutions use algorithmic mechanisms that address a small subset of emerging requirements, often at high-energy performance overhead. Further, side-channel physical attacks can compromise classical solutions. Hardware overcome many these limitations with less energy Nanoelectronics-based hardware preserves advantages while enabling conceptually new primitives applications. This tutorial paper shows how...
Hardware security has emerged as an important field of study aimed at mitigating issues such piracy, counterfeiting, and side channel attacks. One popular solution for hardware attacks are physical unclonable functions (PUF) which provide a specific unique signature or identification. The uniqueness PUF depends on intrinsic process variations within individual integrated circuits. As become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies...
Hardware security has emerged as an important field of study aimed at mitigating issues such piracy, counterfeiting, and side channel attacks. One popular solution for hardware attacks are physical unclonable functions (PUF) which provide a specific unique signature or identification. The uniqueness PUF depends on intrinsic process variations within individual integrated circuits. As become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies...
A compact model and simulation methodology for chalcogenide based memristor devices is proposed. From a microprocessor design view point, it important to be able simulate large numbers of within the integrated circuit architecture in order speed up reliably development process. Ideally, device models would accurately describe characteristic behavior represented by single-valued equations without requiring need recursive or numerically intensive solutions. With this mind, we have developed an...
Hardware security has emerged as an important field of study aimed at mitigating issues such piracy, counterfeiting, and side channel attacks. One popular solution for hardware attacks are physical unclonable functions (PUF) which provide a specific unique signature or identification. The uniqueness PUF depends on intrinsic process variations within individual integrated circuits. As become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies...
This article presents our research towards developing novel and fundamental methodologies for data representation using spike-timing-dependent encoding. Time encoding efficiently maps a signal's amplitude information into spike time sequence that represents the input offers perfect recovery band-limited stimuli. In this article, we pattern neural activities across multiple timescales encode sensory time-dependent temporal scales. The autonomous classification of time-series signatures are...
A compact model and simulation methodology for chalcogenide based memristor devices is proposed. From a microprocessor design view point, it important to be able simulate large numbers of within the integrated circuit architecture in order speed up reliably development process. Ideally, device models would accurately describe characteristic behavior represented by single-valued equations without requiring need recursive or numerically intensive solutions. With this mind, we have developed an...
We developed a spice-compatible compact model of TiO2-TiO2–x memristors based on classic ion transportation theory. Our is shown to simulate important dynamic memristive properties like real-time memristance switching, which are critical in memristor-based analog circuit designs. The model, as well its analytical approximation, validated with the experimentally obtained data from real devices. Minor deviations our measured also analyzed and discussed.
The value memristor devices offer to the neuromorphic computing hardware design community rests on ability provide effective device models that can enable large scale integrated architecture application simulations. Therefore, it is imperative develop practical, functional of minimum mathematical complexity for fast, reliable, and accurate technology simulation. To this end, various have been proposed in literature seeking characterize physical electronic time domain behavioral properties...
Hardware security has emerged as an important field of study aimed at mitigating issues such piracy, counterfeiting, and side channel attacks. One popular solution for hardware attacks are physical unclonable functions (PUF) which provide a specific unique signature or identification. The uniqueness PUF depends on intrinsic process variations within individual integrated circuits. As become more prevalent due to technology scaling into the nanometer regime, novel nanoelectronic technologies...
Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of key components neuromorphic systems is neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding temporal schemes are discussed. Two novel schemes, parallel iteration, presented. The power consumption been significantly reduced by combing iteration low sampling advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both...
Abstract Reservoir computing (RC) has received recent interest because reservoir weights do not need to be trained, enabling extremely low-resource consumption implementations, which could have a transformative impact on edge and in-situ learning where resources are severely constrained. Ideally, natural hardware should passive, minimal, expressive, feasible; date, proposed reservoirs had difficulty meeting all of these criteria. We, therefore, propose that meets criteria by leveraging the...
With the recent advances in memristors as a potential building block for future hardware, it becomes an important and timely topic to study role that may play hardware security. To address this issue, paper presents survey on research activities memristor modelling application of First, we give overview current literature experimentation, characterization, modeling which includes Chua's original theoretical prediction model, more detailed models based implementations, SPICE simulation...
A framework for implementing reservoir computing (RC) and extreme learning machines (ELMs), two types of artificial neural networks, based on 1D elementary Cellular Automata (CA) is presented, in which separate CA rules explicitly implement the minimum computational requirements layer: hyperdimensional projection short-term memory. CAs are cell-based state machines, evolve time accordance with local a cell's current those its neighbors. Notably, simple single cell shift as memory rule fixed...
Biological organisms must learn how to control their own bodies achieve deliberate locomotion, that is, predict next body position based on current and selected action. Such learning is goal-agnostic with respect maximizing (minimizing) an environmental reward (penalty) signal. A cognitive map learner (CML) a collection of three separate yet collaboratively trained artificial neural networks which construct representations for the node states edge actions arbitrary bidirectional graph. In so...
3627 Background: Blood-based colorectal cancer (CRC) screening tests can improve adherence to guidelines. Yet, current commercially available options have poor sensitivity and specificity inhibiting incorporation into routine clinical care. Here we report the validation of a blood-based test for detection advanced neoplasia. Methods: This aims detect neoplasia by identifying tumor-associated biomarkers including genomic or epigenomic (methylation fragmentomics) signatures in cell-free DNA...
The rich computational dynamics coupled with simple training in reservoir computing (RC) algorithms makes them a natural choice for spatiotemporal learning systems embedded platforms. In this article, we study three variants of the algorithm: echo-state network (ESN), liquid-state machine (LSM), and time-delay reservoirs (TDRs). A digital architecture is used as baseline test bed to benchmark epileptic seizure detection. An average accuracy 85% observed across algorithm effectiveness...
This article presents and demonstrates a stochastic logic time delay reservoir design in FPGA hardware. The network approach is analyzed using number of metrics, such as kernel quality, generalization rank, performance on simple benchmarks also compared to deterministic design. A novel re-seeding method introduced reduce the adverse effects noise, which may be implemented other computing designs, echo state networks. Benchmark results indicate that proposed performs well noise-tolerant...