Naushad Manzoor Laskar

ORCID: 0000-0002-4169-0250
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About
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Research Areas
  • Analog and Mixed-Signal Circuit Design
  • Advanced MEMS and NEMS Technologies
  • VLSI and FPGA Design Techniques
  • Mechanical and Optical Resonators
  • CCD and CMOS Imaging Sensors
  • Advanced Memory and Neural Computing
  • Low-power high-performance VLSI design
  • Advancements in Semiconductor Devices and Circuit Design
  • Radio Frequency Integrated Circuit Design
  • Evolutionary Algorithms and Applications
  • VLSI and Analog Circuit Testing
  • Acoustic Wave Resonator Technologies
  • Advanced Multi-Objective Optimization Algorithms
  • Neural Networks and Reservoir Computing
  • Force Microscopy Techniques and Applications
  • Metaheuristic Optimization Algorithms Research
  • Photonic and Optical Devices
  • Neuroscience and Neural Engineering
  • IoT and Edge/Fog Computing
  • IoT-based Smart Home Systems
  • Vehicle Routing Optimization Methods
  • Caching and Content Delivery
  • Advanced MIMO Systems Optimization
  • Innovative Energy Harvesting Technologies
  • Integrated Circuits and Semiconductor Failure Analysis

Vellore Institute of Technology University
2023-2024

National Institute Of Technology Silchar
2015-2022

With the advent of IoT, cloud/fog based healthcare systems have become a growing trend in modern systems. These comprise smart sensors, which on integration with medical devices, generate heterogeneous big data that can be used diagnosis various diseases. However , there is continuous flow large quantity such systems, due to it may face many difficulties. Among pre-requisites for proper functioning these lifetime vital factor. Keeping view aspects, use new hybrid whale-PSO algorithm (HWPSO)...

10.3233/jifs-169957 article EN Journal of Intelligent & Fuzzy Systems 2019-02-08

Evolutionary algorithms are simple and efficient techniques for optimization of VLSI circuits. In this work, Whale Optimization Algorithm (WOA) is used to design a two stage CMOS operational amplifier (OpAmp)with optimum area so as achieve minimum offset voltage also meet different specifications such Slew Rate, Gain etc. the amplifier. For maintaining current imbalance at output OpAmp, minimization an important requirement. Algorithmic results were further validated by redesigning OpAmp in...

10.1080/02522667.2017.1372913 article EN Journal of Information and Optimization Sciences 2017-11-10

A Low Power, Noise Neural Amplifier is designed in this paper. Folded Cascode Operational Transconductance (OTA) with self-biased cascode current mirror load used. Current Scaling and other low noise design techniques are employed to achieve the input referred power dissipation. The amplifiers bandwidth can be adjusted record either local field potentials or neural spikes by controlling bias current. Simulations were performed Cadence Virtuoso using SCL 180nm technology parameters....

10.1109/edssc.2017.8333234 article EN 2017-10-01

In the VLSI Physical Design Stage, Floorplanning is an essential step, as it effective means to manage circuit design complexity, which increasing with advancement in technology. involves determining locations, shape, size of modules a chip and such estimates area, delay wiring congestion, thereby providing ground work for layout. Computationally, NP hard problem. So many researchers from time have suggested various heuristics metaheuristic approaches solving Floorplan Problem. The...

10.1109/iciiecs.2015.7192989 article EN 2015-03-01

A Low Voltage, Power, Noise and High Gain Two Stage OpAmp configuration utilizing self-cascoding transistors has been proposed. Self cascoding helps in decrease of Channel Length Modulation Effect aides accomplishing high output impedance voltage swing, thereby improving the gain. The frequency response proposed design makes it conceivable to be utilized as a part Frequency Applications. For enhancing Phase Margin design, zero nulling active resistor implemented Transmission Gates for...

10.1109/devic.2017.8073949 article EN 2019 Devices for Integrated Circuit (DevIC) 2017-03-01

For enhancing the performance of any analog circuit, a good current mirror must be designed for copying from one active device to other. In this proposed work, we have come up with modified structure based on Flipped Voltage Follower Cell, which improves dynamic range without trading off other parameters. Simulations were performed in Cadence Spectre using UMC 180nm technology files and specifications compared reported high mirrors. Comparative analysis shows that has very as mirrors, while...

10.1109/devic.2017.8073959 article EN 2019 Devices for Integrated Circuit (DevIC) 2017-03-01

Implantable medical devices have revolutionized healthcare by providing continuous monitoring and therapeutic interventions within the human body. The overall performance of these is heavily dependent on effectiveness efficiency integrated electronic components, such as transistors. This survey explores growing utilization Tunnel Field-Effect Transistors (TFETs) in implantable devices, shedding light their advantages challenges this specific application domain. TFETs, characterized unique...

10.1080/03772063.2024.2412790 article EN IETE Journal of Research 2024-10-21

In emulating biological behavior of vertebrates, neuromorphic integrated chips are being widely employed. CMOS Winner-Takes-All (WTA) circuit is one the key component chips. The modelling WTA has been carried out and few modern Evolutionary Optimization algorithms have also employed to optimize parameters in order improve slew rate. Simulations for optimization were performed using MATLAB. results found compared with each other. Based on optimized results, designed Cadence Virtuoso simulated...

10.1080/02522667.2017.1372133 article EN Journal of Information and Optimization Sciences 2017-08-18
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