This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, circuit employs three linearization techniques: bulk-driven (BD), source degeneration, and input attenuation created by MI metal-oxide-semiconductor transistor technique (MI-MOST). Although techniques result in reduced dc gain, self-cascode transistors are used to boost gain of MI-OTA. Furthermore, MI-MOST...

Using the Gm‐C compensation technique, an ultra‐low‐power two‐stage operational transconductance amplifier (OTA) with rail‐to‐rail input/output swing is presented. The input stage of proposed OTA has benefit enhancement compared to conventional same power consumption and silicon area. Simulation results in a 0.18 μm CMOS technology show DC gain 9.5 dB as well 88% improvement bandwidth folded cascode structure.

This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. method also increases transconductance of amplifier times against conventional one. enhanced topology is merged with using cross-coupled connections significantly increase transconductance. These circuitry ideas lead an improvement in amplifier's...

<title>Abstract</title> This paper presents a novel design methodology for transimpedance amplifier (TIA) featuring low input resistance. The resistance of the proposed TIA is achieved through implementation various analog circuit techniques, such as regulated cascode (RGC) and flip voltage follower (FVF), further enhanced by advantages BiCMOS technology. A key characteristic its ability to maintain consistently impedance across high frequencies without exhibiting inductive behavior or...

A single‐stage multi‐path operational transconductance amplifier (OTA) is presented. The proposed uses the enhancing technique in an upgraded folded cascode (FC) amplifier. It significantly improves DC gain, unity‐gain bandwidth and slew rate compared with previous FC amplifiers same power consumption. Simulation results 90 nm complementary metal‐oxide semiconductor (CMOS) technology show that OTA achieves a 59.1 dB gain of 650 MHz, which makes it suitable for fast‐settling...

Summary This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation to enhance under reasonable stability. Combining these approaches leads an ultra‐low‐power high performance without increasing power dissipation compared the conventional one. Simulation results 0.13‐µm complementary...

This paper presents a low-voltage nano-power multiple-input operational transconductance amplifier (MI-OTA) with high linearity performance and increased input voltage swing. The enhanced performances are achieved thanks to employing several techniques as the bulk-driven, source-degeneration, self-cascode negative conductance along concept of signal attenuation formed by MOS transistor. MI-OTA is widely tunable that serves for biological signals processing. A 3 <sup...

This paper presents a bulk-driven current mirror circuit based on the gain-boosting technique to achieve high input/output dynamic range and output resistance. The diode-connected transistor at input removes threshold voltage limitation provide low headroom basic transistors. In addition, auxiliary used in first structure is mode amplifier that driven by draining from main remove swing. order higher resistance, second includes without creating any Simulation results 0.18 ​μm CMOS technology...

This work presents a tail-less fully differential bulk-driven transconductance amplifier without using common-mode feedback (CMFB) circuit. The proposed employs two P-type and N-type current mirrors to form self-biasing positive loops resulting in double transconductance. bulk terminals of the are used as input nodes provide high dynamic range. diode-connected topologies adaptively bias other transistors cover lack CMFB To ensure stability, additional sources paralleled with structures. A...

In this paper, a weak inversion technique for recycling folded cascode (RFC) and (FC) operational amplifier design with flicker noise reduction is presented. Flicker the dominant source in silicon MOSFET's especially low frequency. A new formulation input referred region also presented an efficient tradeoff between refereed power frequency response performed optimum region. This procedure will be useful all of CMOS amplifiers. The proposed significantly enhances conventional performance FC...

A new adaptive biased cascode current mirror is presented. The proposed has advantage of simplicity with low voltage operation without using any other bias currents or voltages. With self-biasing configuration, large dynamic input high accuracy can be maintained increasing resistance limiting output swing. Also, the incorporated in folded amplifier order to enhance its phase margin (PM). Enhanced PM Folded Cascode unity gain bandwidth 84 MHz and consumes 720 μW @ 1.8 V 88 . circuits are...

A new ultra-low power fully recycling folded cascode amplifier with low supply voltage is presented. The configuration benefits from higher transconductance, slew rate and gain in comparison conventional cascode. Furthermore, the phase-margin enhanced input referred noise reduced this configuration. Simulation results standard 0.18 μm CMOS technology shows that proposed achieves 316% improvement bandwidth 11 dB boosts DC amplifier. consumes 240nW @ 0.6 V which make it suitable for low-power...

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of structure, positive feedback and feed-forward path. In comparison with the typical CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate common mode rejection ratio (CMRR). presented OTA simulated in 0.18-μm technology simulation results confirm theoretical analyses....

This brief studies the current mismatch of MOS transistors operating in weak inversion region. Explicit formulas are derived from drain-current relationship a long-channel transistor. By referring variance to gate terminal under small-signal conditions, dependence gate-source voltage on design parameters and sources can be considered. will help designers choose optimum sizes efficient gm/I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub>...

This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and mirror-based paths, are combined to increase the transconductance, thus leading larger dc gain higher bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells employed variable sources provide class-AB operation adaptive biasing of all other drivers. The proposed...

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with structure. The proposed has pipelining scheme it designed symmetrically in three stages repeatable Thus, power consumption, chip area the number of control signals reduced. DAC simulated 0.18-μm CMOS technology spurious-free dynamic range (SFDR) 65.3...