A5057014407- Low-power high-performance VLSI design
- Analog and Mixed-Signal Circuit Design
- Advanced Memory and Neural Computing
- Advanced Wireless Communication Techniques
- Error Correcting Code Techniques
- Advancements in PLL and VCO Technologies
- Digital Filter Design and Implementation
- Ferroelectric and Negative Capacitance Devices
- Advancements in Semiconductor Devices and Circuit Design
- Embedded Systems Design Techniques
- Radiation Effects in Electronics
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices
- Advanced Data Compression Techniques
- Advanced Neural Network Applications
- CCD and CMOS Imaging Sensors
- Advanced Adaptive Filtering Techniques
- Coding theory and cryptography
- Interconnection Networks and Systems
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
- Adversarial Robustness in Machine Learning
- Power Line Communications and Noise
- Radio Frequency Integrated Circuit Design
- Optical Network Technologies
University of Illinois Urbana-Champaign
2015-2024
Urbana University
1998-2008
Texas Instruments (United States)
2006
University of Minnesota
1991-2003
Wright State University
1990-2002
AT&T (United States)
1994-2002
Nokia (United States)
1993-2002
Alcatel Lucent (Germany)
2002
University of Dayton
2002
University of Illinois System
2001
Sensitive sensing Neonatal care, particularly for premature babies, is complicated by the infants' fragility and need a large number of tethered sensors to be attached their tiny bodies. Chung et al. developed pair that only require water adhere skin allow untethered monitoring key vital signs (see Perspective Guinsburg). On-board data processing allowed efficient wireless near-field communication using standard protocols. The absence cables makes it easier handle infants allows skin-to-skin...
A high-throughput memory-efficient decoder architecture for low-density parity-check (LDPC) codes is proposed based on a novel turbo decoding algorithm. The benefits from various optimizations performed at three levels of abstraction in system design-namely LDPC code design, algorithm, and architecture. First, the interconnect complexity problem current implementations mitigated by designing architecture-aware having embedded structural regularity features that result regular scalable...
A multi-functional in-memory inference processor integrated circuit (IC) in a 65-nm CMOS process is presented. The prototype employs deep architecture (DIMA), which enhances both energy efficiency and throughput over conventional digital architectures via simultaneous access of multiple rows standard 6T bitcell array (BCA) per precharge, embedding column pitch-matched low-swing analog processing at the BCA periphery. In doing so, DIMA exploits synergy between dataflow machine learning (ML)...
Embedded sensory systems (Fig. 31.2.1) continuously acquire and process data for inference decision-making purposes under stringent energy constraints. These always-ON need to track changing statistics environmental conditions, such as temperature, with minimal consumption. Digital architectures [1,2] are not well-suited energy-constrained due their high consumption, which is dominated (>75%) by the cost of memory read accesses digital computations. In-memory [3,4] significantly reduce...
New high-speed VLSI architectures for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm are presented in this paper. The speed bottleneck is iterative computation of discrepancies followed by updating error-locator polynomial. This eliminated via a series algorithmic transformations that result fully systolic architecture which single array processors computes both and error-evaluator polynomials. In contrast to conventional critical path passes through two multipliers...
In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond critical imposed by requirement to match path delay throughput. This deliberate introduction of input-dependent errors leads degradation in algorithmic performance, which compensated via noise-tolerance (ANT) schemes. The resulting setup that comprises DSP architecture operating at subcritical and error control scheme referred as soft DSP. effectiveness proposed...
This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These are suited high-capacitance buses where extra power dissipation due encoder and decoder circuitry is offset by savings at bus. In this framework, data source (characterized in probabilistic manner) first passed through decorrelating function f/sub 1/. Next, variant entropy 2/ employed, which reduces The then employed derive novel encoding whereby practical forms 1/ proposed....
This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced errors in latches and flip-flops. The presented error-correcting latch flip-flop designs are power efficient, introduce minimal speed penalty, employ reuse of on-chip scan design-for-testability design-for-debug resources to minimize area overheads. Circuit simulations using sub-90-nm technology show that the achieve more than 20-fold reduction cell-level rate (SER). Fault injection...
In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires replica whose output can be employed the corrected in case original system computes erroneously. When combined with voltage overscaling (VOS), resulting soft digital signal processing achieves up 60% and 44% energy savings no loss signal-to-noise ratio (SNR) for receive filtering QPSK butterfly of fast Fourier transform (FFT) WLAN OFDM system,...
In this paper, we propose a framework for low-energy digital signal processing (DSP) where the supply voltage is scaled beyond critical required to match path delay throughput. This deliberate introduction of input-dependent errors leads degradation in algorithmic performance, which compensated via noise-tolerance (ANT) schemes. The resulting setup comprised DSP architecture operating at sub-critical and error control scheme referred as soft DSP. It shown that technology scaling renders...
A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The implements the turbo-decoding message-passing (TDMP) algorithm architecture-aware (AA-)LDPC which has a faster convergence rate hence throughput advantage over standard decoding algorithm. It employs reduced complexity message computation mechanism free of lookup tables, features programmable network interleaving based on code structure. decodes any mix...
Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from communication-theoretic view bus jointly address delay, reliability. framework, the data is first passed through nonlinear source coder reduces self coupling transition activity imposes constraint on...
In this paper, we propose the concept of compute memory, where computation is deeply embedded into memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute exploits relaxed precision linearity requirements pattern recognition applications. System-level simulations incorporating various deterministic errors from chain demonstrates limited accuracy processing does not significantly degrade system performance, which means probability detection...
Stochastic computation, as presented in this paper, exploits the statistical nature of application-level performance metrics, and matches it to attributes underlying device circuit fabrics. Nanoscale fabrics are viewed noisy communication channels/networks. Communications-inspired design techniques based on estimation detection theory proposed. computation advocates an explicit characterization exploitation error statistics at architectural system levels. This paper traces roots stochastic...
This paper presents a robust deep in-memory machine learning classifier with stochastic gradient descent (SGD)-based on-chip trainer using standard 16-kB 6T SRAM array. The architecture (DIMA) enhances both energy efficiency and throughput over conventional digital architectures by reading multiple bits per bit line (BL) read cycle employing mixed-signal processing in the periphery of bit-cell Though these techniques improve latency, DIMA's analog nature makes it sensitive to process,...
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the power consumption. The coupling-driven invert method use slim encoder decoder architecture hardware overhead. Experimental results indicate that our methods save effective as much 30% an 8-bit with one-cycle redundancy.
We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on modeling analysis-based approach that employs judicious mix of probability theory, circuit simulation, graph theory fault simulation. achieves five orders magnitude speed-up over Monte Carlo simulation approaches with less than 5% error. Dependence (SER) circuits supply voltage, clock period, latching window, topology, input vector values are explicitly captured studied typical...
Presented in this paper are: 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept noise tolerance via coding for achieving efficiency presence noise. In particular, a) circuit speed f/sub c/ supply voltage V/sub dd/; b) transition activity t noise; c) dynamic dissipation; d) total (dynamic static) dissipation are derived. A surprising result is that a scenario where component power dominates, minimum operation (V/sub dd, opt/) greater than...
We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on modeling approach that employs judicious mix of probability theory, circuit simulation, graph fault simulation. achieves five orders magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence the soft-error rate (SER) logic circuits supply voltage, clock period, latching window, topology, input vector explicitly captured studied typical...
In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic error-tolerance (ASET), employs low-complexity estimators of a main DSP block achieve reliable operation in the presence errors. Three distinct ASET - spatial, temporal and spatio-temporal- are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that provide robustness error rates up P/sub...
This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural circuit techniques are proposed to address the dominant energy delay costs associated with data movement in CNNs. The employs a deep in-memory architecture, embed low swing mixed-signal computations periphery of SRAM bitcell array. An efficient access pattern multiplier exploit reuse opportunities convolution. Silicon-validated energy, delay, behavioral models...
Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared conventional maximum-likelihood decoding. However, lack any structural regularity in these essentially random is a major challenge for building practical low-power LDPC decoder. In this paper, we jointly design code and decoder induce needed reduced complexity parallel architecture. This interconnect-driven approach eliminates need complex...
A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl times/ 360 mu/m) and low power (280 mW). analog equalizer as an 8-way interleaved, 4-tap discrete-time linear filter. improved the data rate of a 102 cm backplane interconnect by 110%. On-die logic determines optimal receiver settings through comparator offset cancellation, alignment transmitter receiver,...
Capacitive crosstalk between adjacent wires in long on-chip buses significantly increases propagation delay the deep submicron regime. A high-speed bus can be designed by eliminating through encoding. In this paper, we present an overview of existing coding schemes and show that they require either a large wiring overhead or complex encoder-decoder circuits. We propose family codes referred to as overlapping reduce both overheads. construct two from demonstrate their superiority over terms...