A5077008357- CCD and CMOS Imaging Sensors
- Advanced Optical Sensing Technologies
- Electrostatic Discharge in Electronics
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Analytical Chemistry and Sensors
- Electromagnetic Compatibility and Noise Suppression
- Advanced Fluorescence Microscopy Techniques
- Sparse and Compressive Sensing Techniques
- Analog and Mixed-Signal Circuit Design
- Tactile and Sensory Interactions
- Ocular and Laser Science Research
- VLSI and Analog Circuit Testing
- Gaze Tracking and Assistive Technology
- 3D IC and TSV technologies
- Image Processing Techniques and Applications
- Thin-Film Transistor Technologies
- Hand Gesture Recognition Systems
Samsung (South Korea)
2016-2023
University of Illinois Urbana-Champaign
2012-2016
Korea University
2000
Conventional CMOS charge pump circuits have some current mismatching characteristics. The mismatch of the in PLLs generates a phase offset, which increases spurs PLL output signals. In particular, it reduces locking range wide with dual loop scheme. A new circuit perfect matching characteristics is proposed. By using an error amplifier and reference sources, one can achieve good It shows nearly over whole VCO input range, amount spur < –75 dBc signal. implemented 0.25 µm process.
In this paper, we propose the concept of compute memory, where computation is deeply embedded into memory (SRAM). This deep embedding enables multi-row read access and analog signal processing. Compute exploits relaxed precision linearity requirements pattern recognition applications. System-level simulations incorporating various deterministic errors from chain demonstrates limited accuracy processing does not significantly degrade system performance, which means probability detection...
A video graphics array (VGA) (640 × 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7-μm global-shutter pixel in 65-nm back-side illumination (BSI) process. With a structure, we achieved motion artifact-free depth map. Peak current during exposure time reduced by spreading constant delay chain the photo-gate driver. Column fixed-pattern phase noise (FPPN) from is self-compensated proposed time-interleaving technique two inversely directional clock chains...
The evolution of 3D depth-sensing technology enables various applications in mobile devices, from conventional photography enhancement (e.g., autofocus and bokeh effect) to new such as augmented reality scanning. Usually, depth sensors operate with RGB color for image fusion; the spatial resolution should be compatible that better fusion quality, which requires mega-pixel sensors. Among different techniques, only indirect time-of-flight (ToF) can generate higher maps smaller system cost...
In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation deeply embedded into the (SRAM). Behavioral models incorporating CM's circuit non-idealities in 45nm SOI CMOS are presented. System-level simulations using these demonstrate that probability of handwritten digit recognition P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper presents an energy-efficient VLSI implementation of Sparse Distributed Memory (SDM). High throughput and Hamming distance-based address decoder (CM-DEC) is proposed by employing compute memory [1], where computation deeply embedded into a (SRAM). Hierarchical binary decision (HBD) also to enhance area- energy-efficiency read operation minimizing data transfer. The SDM employed as auto-associative with four iterations 16×16 noisy input image error rates 15%, 25%, 30%. achieves 39×...
A 1.2-Mpixel indirect time-of-flight (ToF) CMOS image sensor is presented to lower peak current and cancel out multi-user interference. The proposed 4-tap 3.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> demodulation pixel optimally designed improve quantum efficiency (QE) contrast (DC). new “multiple-interleaving” scheme reduce the self-compensate...
A 640 × 480 indirect Time-of-Flight (ToF) CMOS image sensor has been designed with 4-tap 7-μm global-shutter pixel in 65-nm back-side illumination (BSI) process. With novel structure, we achieved motion artifact-free depth map. Column fixed-pattern phase noise (FPPN) is reduced by introducing alternative control of the clock delay propagation path photo-gate driver. As a result, artifact and column FPPN are not noticeable The proposed ToF shows less than 0.62% 940-nm illuminator over working...
Analog-to-digital converter (ADC)-based multi-Gb/s serial link receivers have gained increasing attention in the backplane community due to desire for higher I/O throughput, ease of design portability, and flexibility. However, power dissipation such is dominated by ADC. ADCs links employ signal-to-noise-and-distortion ratio (SNDR) effective-number-of-bit (ENOB) as performance metrics these are standard generic ADC design. This paper studies use information-based bit-error-rate (BER) a...
This paper presents a CMOS image sensor with $2.1\ \mu \mathrm{m}$ pixel for automotive applications. By using sub-pixel structure and high-capacity DRAM capacitor per pixel, single exposure dynamic range achieves 140 dB at $85 ^{\circ}\mathrm{C}$, supporting LED flicker mitigation. Dual conversion gain circuits of small photodiode enable SNR to stay above 23 $105 ^{\circ}\mathrm{C}$ even the very high capacitance. The full-depth deep trench isolation prevents electrical crosstalk between...
The inter-die signal interfaces in a 3D-IC are vulnerable to over-voltage stress induced by Charged Device Model ESD. magnitude of the is highly sensitive design ground distribution network on both die and package level. It also affected type being used. Small voltage clamping devices may be placed at receivers mitigate risk gate dielectric breakdown. New ESD rule checking tools needed for automation.
A 2.8μm 4-tap global shutter pixel has been realized for a compact and high-resolution time of flight (ToF) CMOS image sensor. 20,000 e- high full-well capacity (FWC) per tap is obtained by employing supplementary MOS capacitor. 36% quantum efficiency (QE) achieved backside scattering technology (BST) thick silicon process. In addition, demodulation contrast (DC) improved to 86 % additional deep photodiode doping process static potential gradient in photodiode.
An inherent CDM-electrostatic discharge (ESD) hazard exists in T-coil circuits due to magnetic coupling from the pad receiver input. "inductance halving" technique is proposed reduce during ESD, thereby canceling voltage overshoot. Receiver with continuous-time linear equalizers are placed on a 65-nm CMOS test chip evaluate performance of comparison conventional secondary ESD protection. From eye diagram using 25-Gb/s pseudorandom bit sequence data, an inductance-halving shows 1.8× higher...
An automotive 2.1 μm CMOS image sensor has been developed with a full-depth deep trench isolation and an advanced readout circuit technology. To achieve high dynamic range, we employ sub-pixel structure featuring conversion gain of large photodiode lateral overflow small connected to in-pixel storage capacitor. With the sensitivity ratio 10, expanded range could reach 120 dB at 85 °C by realizing low random noise 0.83 e- capacity 210 ke-. over 25 signal-to-noise is achieved during HDR...
An indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7 μm global shutter pixel in back-side illumination process. 15000 e- of high full-well capacity (FWC) per a tap 3.5 pitch and 3.6 read-noise realized by employing true correlated double sampling (CDS) structure storage gates (SGs). Noble characteristics such as 86 % demodulation contrast (DC) at 100MHz operation, 37 higher quantum efficiency (QE) lower parasitic light sensitivity (PLS) 940 nm have...
An inherent CDM hazard exists in T-coil circuits due to magnetic coupling. "inductance halving" technique is proposed reduce coupling during ESD. From simulation, the solution can effectively suppress voltage overshoot and minimize bandwidth degradation, compared conventional secondary ESD protection.
Adaptive active bias conditioning (AABC) is proposed for high-speed inputs/outputs (I/O) to mitigate the tradeoff between bandwidth and electrostatic discharge (ESD) reliability. During a component-level ESD event, I/O transistors' gate voltages are adaptively set values that maximize robustness based on polarity. The AABC technique has no deleterious effect signal integrity or power consumption, because its circuitry located off path activated only during ESD. efficacy of protection scheme...
Modern electronic devices have been designed to allow many types of human-machine interfaces with flexibility. One the user-friendly navigations is interfacing a human hand, but implementation using conventional devices, such as additional controllers or image sensors, requires larger size higher power. In this paper, small-size and low-power 3D touchless hand navigation sensor (HNS) presented. The proposed HNS based on proximity consists an LED integrated photosensors. x- y-directions can...