A5017988858- Energy Harvesting in Wireless Networks
- Innovative Energy Harvesting Technologies
- Semiconductor materials and devices
- Wireless Power Transfer Systems
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Advancements in PLL and VCO Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor Lasers and Optical Devices
- Advanced DC-DC Converters
- Radio Frequency Integrated Circuit Design
- Parallel Computing and Optimization Techniques
- Advanced Thermoelectric Materials and Devices
- Photonic and Optical Devices
- Advanced Battery Technologies Research
National Cheng Kung University
2024
ARM (United Kingdom)
2019-2021
Taiwan Semiconductor Manufacturing Company (Taiwan)
2021
University of Cambridge
2015-2018
National Yang Ming Chiao Tung University
2014
A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well single-pattern backend flow for the first time. High performance exhibit 57%/87% higher NMOS/PMOS drive current compared to previously reported 22nm [1]. New devices are introduced reduce bit cell leakage by 28x a regular SRAM enabling new 6T low-leakage with of sub 1pA/cell. An device optimized layout shows excellent f <inf...
This paper presents a 100 mV input, 500 output single-inductor multiple-output (SIMO) based step-up dc-dc converter with adaptive gate biasing (AGB) technique implemented in 0.18 μm CMOS technology for thermoelectric energy harvesting. The proposed AGB and near-threshold voltage (near- VTH) redistribution control (ERC) ensure high conversion efficiency over wide range of load currents. method automatically reduces conduction switching losses power MOSFETs without the need auxiliary...
Recent research has shown subthreshold operation to reduce active energy in low-power MCUs [1], [2], [5]. However, some applications impose additional constraints. For battery-powered sensor nodes deployed remote locations, the MCU may lie dormant for long periods, only waking up when a detects activity. such cases, needs very low sleep power maximize battery lifetime, deterministic real-time response capture rare events, and energy-efficient with enough compute memory run useful workloads....
This paper presents a low-input-voltage (100 mV), low-output-voltage (500-600 mV) thermoelectric energy harvesting interface circuit for near-threshold energy-efficient Internet-of-Things (IoT) devices. The capacitive bootstrapping technique is used to generate positive and negative bias pair alleviating the significant conduction losses of power MOSFETs in operation. Internal voltages are automatically boosted different levels as per loading conditions extend output range. deployment...
This article presents the control circuit of a power converter that regulates computing speed digital circuit. The proposed implements delay regulation line (DDL) matched with ring oscillator (RO) clocks subsystem. supply voltage subsystem so propagation through DDL matches time reference. Consequently, frequency RO tracks and keeps controlled value over process, voltage, temperature (PVT). A 65-nm CMOS prototype validates method. includes an Arm Cortex-M33 CPU memories optimized for...
Energy harvesting techniques have been developed more than a decade and received much attention in realizing long-term energy autonomous microsystems. Many converter topologies circuit reported to effectively convert the harvested usable outputs. In this paper, major green sources as well equivalent circuits are reviewed. addition, maximum power point tracking (MPPT) technique conversion also included.
The pulse-width modulated (PWM) switching rectification that can achieve a high power factor (PF) for increasing the energy transfer efficiency between an LC resonator and rectifier voltage step-up -down conversion is proposed wireless (WPT) receiver. method emulate as resistive load by using inductor integrated phase synchronizers. Additionally, similar to switched-inductor converter controls duty cycle ratio (D), PWM control output VOUT when input rectified, wirelessly coupled instead of...
The lower bound on the power expended by an RC relaxation oscillator is decided network. This can be minimized reducing oscillation swing and increasing R. In former technique, tighter comparator constraints limit benefits while latter technique increases resistor thermal noise bounding long-term jitter. To this end, letter presents a fully integrated with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network used minimize drop-out loss. Full...
The lower bound on the power expended by an RC relaxation oscillator is decided network. This can be minimized reducing oscillation swing and increasing R. In former technique, tighter comparator constraints limit benefits while latter technique increases resistor thermal noise bounding long-term jitter. To this end, letter presents a fully integrated with core voltage aggressively scaled to subthreshold levels. A self-clocked switched-capacitor network used minimize drop-out loss. Full...
This paper presents a 16Kb antifuse macro in 5nm high-K, metal-gate FinFET CMOS for the first time. Bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are proposed to lower intrinsic bit-error-rate (BER) below 1ppm in-field programming, achieves 10 years of data retention at 125∘C.
This paper investigates a high power factor switch-based wireless transfer front-end circuit for heterogeneous systems. uses an integrated switching rectifier, implemented in 0.18um 1.8V/5V CMOS process. An pair of phase synchronizers is used to align the waveshape wirelessly-coupled sinusoidal voltage source receiving coil corresponding conducting current. Using this approach, can be increased above 0.9 without requiring any or wired feedback transmitter. The rectifier also provide: ac-dc...
A 16Kb one-time-programmable (OTP) antifuse memory is fabricated in a 5nm high-K, metal-gate FinFET CMOS for the first time. The bootstrap high voltage scheme (BHVS), read endpoint detection (REPD) and pseudo-differential sensing (PDS) are implemented to achieve intrinsic bit error rate (BER) below 1ppb in-field programming SoC 10 years of data retention at 125°C.
Ultra-efficient compute combined with UHF RFID has the potential of enabling long-range long-life sensor systems. Standards compatibility in such systems can leverage existing connectivity infrastructure while providing necessary sensory intelligence without burden batteries or active radios. Figure 1 shows scheme for EPC class Gen2 standard (C1G2) [1], wherein interrogator (RDR) initiates a continuous RF wave (CW) followed by Query Select command. The compatible system harvests energy from...