- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Silicon and Solar Cell Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Photolithography Techniques
- Ion-surface interactions and analysis
- Ancient Near East History
- Metal and Thin Film Mechanics
- 3D IC and TSV technologies
- Silicon Carbide Semiconductor Technologies
- Copper Interconnects and Reliability
- Linguistics and language evolution
- VLSI and Analog Circuit Testing
- Eurasian Exchange Networks
- Plasma Diagnostics and Applications
- Low-power high-performance VLSI design
- Archaeology and Historical Studies
- Advanced Surface Polishing Techniques
- Ancient Egypt and Archaeology
- Thin-Film Transistor Technologies
- Electron and X-Ray Spectroscopy Techniques
- Nanowire Synthesis and Applications
- Surface Roughness and Optical Measurements
- VLSI and FPGA Design Techniques
- Semiconductor materials and interfaces
Philipps University of Marburg
2010-2024
Fraunhofer Institute for Integrated Systems and Device Technology
2010-2022
HAW Hamburg
2006-2022
Deutsche Nationalbibliothek
2019
Leibniz University Hannover
2019
State Education and Research Institute for Viticulture and Pomology Weinsberg
2019
Schott (Germany)
2004-2018
Fraunhofer Society
1985-2014
TU Wien
2008
Dienstleistungszentrum Ländlicher Raum
2007
We present "design rules" for the selection of molecules to achieve electronic control over semiconductor surfaces, using a simple molecular orbital model. The performance most devices depends critically on their surface properties, i.e., band-bending and recombination velocity. For semiconductors, these properties depend density energy distribution states. model is based state-molecule, HOMO-LUMO-like interaction between molecule semiconductor. test it by combination contact potential...
The corner effect is known as a leakage current enhancement at the edges of active areas in shallow trench isolated CMOS transistors. It usually deteriorates transistor performance. In this work, for FinFET transistors with minimum feature size 50 nm investigated by coupled three-dimensional process and device simulation. contrast to earlier generations, small FinFETs typical parameters does not lead an additional therefore deteriorate This holds both double triple gate FinFETs.
Process variations increasingly challenge the manufacturability of advanced devices and yield integrated circuits. Technology computer-aided design (TCAD) has potential to make key contributions minimize this problem, by assessing impact certain on device, circuit, system. In way, TCAD can provide information necessary decide investments in processing level or adoption a more variation tolerant process flow, device architecture, circuit chip level. Five Fraunhofer institutes joined forces...
A new two-dimensional process modeling program written in Fortran is described. For the first time, this allows simulation of all important processing steps occurring typical sequences involved fabrication integrated circuits such as doping, oxidation, lithography, etching, and layer deposition. The possesses a modular structure to allow for easy changing improvement models well mathematical procedures. menu driven make it use non-experts readily usable with different computer systems.
A new method for the acceleration of two- and three-dimensional Monte Carlo simulation ion implantation into crystalline targets is presented. The trajectory split ensures a much better statistical representation in regions with dopant concentration several orders magnitudes smaller than maximum. As result, time required to perform comparable accuracy drastically reduced. advantages approach have been confirmed by thorough analysis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A new method for three-dimensional (3-D) simulation of low pressure chemical vapor deposition (LPCVD) in arbitrary geometries using a segment-based topography discretization with triangles, combined redistribution model reactive particles, is presented. Simulation results different like rectangular and rotational symmetric holes are shown. The step coverage predicted by 3-D simulations compared to from 2-D simulations. calculated significantly smaller than Therefore, necessary the accurate...
A new two-dimensional process modeling program written in Fortran is described. For the first time, this allows simulation of all important processing steps occuring typical sequences involved fabrication integrated circuits such as doping, oxidation, lithography, etching, and layer deposition. The possesses a modular structure to allow for easy changing improvement models well mathematical procedures. menu driven make it use non-experts readily usable with different computer systems.
Current advanced transistor architectures, such as FinFETs and (stacked) nanowires nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical systematic process variations have critically influenced device circuit performance. Three-dimensional architectures make the control optimization of geometries even more important, in view nominal electrical performance to be achieved its variations. In turn, it is essential accurately...
Process variations increasingly challenge the manufacturability of advanced devices and yield integrated circuits. Technology computer-aided design (TCAD) has potential to make key contributions minimize this problem, by assessing impact certain on device, circuit, system. In way, TCAD can provide information necessary decide investments in processing level or adoption a more variation tolerant process flow, device architecture, circuit chip level. first two consecutive papers, sources state...
Advanced CMOS devices are increasingly affected by various kinds of process variations. Whereas the impact statistical variations such as Random Dopant Fluctuations has for several years been discussed in numerous publications, effect systematic which result from non-idealities equipment used or layout issues got much less attention. Therefore, first part this paper, an overview sources variability is given. In order to assess and minimize on device circuit performance, relevant must be...
This paper describes the use of thick film heating elements in domestic appliances, and comparison is made performance cost between traditional heaters. Thick films are created by screen printing pastes, usually containing glass metal powders, onto a flat substrate. A brief explanation technology given. has been used for many years electronics industry to produce circuits conductors, resistors dielectrics. The structure resistor makes it ideal applications, may be deposited on number...
Abstract The problem of the time‐optimal flight a glider through given thermal is treated with calculus variations. resulting two‐point boundary value solved using multiple shooting method. Solutions are obtained for various parameter values. For special values these parameters, branching solutions observed. Additional which control variable and normal load factor constrained by their maximum allowed
In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different models were used to simulate long channel silicon on insulator field effect transistors. The results compared results, which taken from the literature. A calibrated parameter set dynamic NonLocal-Tunneling model is presented, qualitatively reproduces at different electrostatic potential conditions and physical gate lengths.
An efficient approach is presented and demonstrated which enables the simultaneous simulation of impact several sources process variations, ranging from equipment-induced to stochastic ones, are caused by granularity matter. Own software combined with third-party tools establish a hierarchical sequence equipment circuit level. Correlations occur because some variability affect different devices device quantities can be rigorously studied.
This paper presents a TCAD based design technology co-optimization (DTCO) process for 14nm SOI FinFET SRAM, which employs an enhanced variability-aware compact modeling approach that fully takes and lithography simulations their impact on 6T-SRAM layout into account. Realistic double patterned gates fins impacts are taken account in the development of model. Finally, global induced variability local statistical evaluated at transistor SRAM levels.
The impact of systematic process variations on the pattering for manufacturing fin field effect transistors (FinFET) has been studied by means physical-based lithography and topography simulation. To this end, a typical sequence static random-access memory (SRAM) cell consisting six simulated. Within sequence, self-aligned double (SADP) is used to create pattern litho-etch-litho-etch (LELE) applied structure gate electrodes. Based resulting from process, frequency distributions width length...
Neck shrivel is a physiological disorder of european plum ( Prunus × domestica L.) fruit, characterized by shriveled pedicel end and turgescent stylar end. Affected fruit are perceived as poor quality. Little known the mechanistic basis neck shrivel, but microcracking cuticle has been implicated. The objective our study was to quantify transpiration through skin surfaces plums with without symptoms shrivel. Cumulative increased linearly time greater in susceptible cultivar Hauszwetsche Wolff...