Roland Jancke

ORCID: 0000-0001-8857-6132
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About
Contact & Profiles
Research Areas
  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • VLSI and FPGA Design Techniques
  • Integrated Circuits and Semiconductor Failure Analysis
  • VLSI and Analog Circuit Testing
  • Low-power high-performance VLSI design
  • Probabilistic and Robust Engineering Design
  • Flexible and Reconfigurable Manufacturing Systems
  • Physics and Engineering Research Articles
  • Advancements in Photolithography Techniques
  • Engineering and Materials Science Studies
  • Radiation Effects in Electronics
  • Embedded Systems Design Techniques
  • Real-time simulation and control systems
  • Electronic Packaging and Soldering Technologies
  • Safety Systems Engineering in Autonomy
  • Statistical and Computational Modeling
  • Wireless Sensor Networks for Data Analysis
  • Simulation Techniques and Applications
  • 3D IC and TSV technologies
  • Green IT and Sustainability
  • Engine and Fuel Emissions
  • Heat Transfer and Optimization
  • Power System Reliability and Maintenance
  • Machine Fault Diagnosis Techniques

Fraunhofer Institute for Integrated Circuits
2005-2023

Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS
2011-2022

TU Wien
2014

Fraunhofer Society
2006-2011

Process variations increasingly challenge the manufacturability of advanced devices and yield integrated circuits. Technology computer-aided design (TCAD) has potential to make key contributions minimize this problem, by assessing impact certain on device, circuit, system. In way, TCAD can provide information necessary decide investments in processing level or adoption a more variation tolerant process flow, device architecture, circuit chip level. Five Fraunhofer institutes joined forces...

10.1109/ted.2011.2150226 article EN IEEE Transactions on Electron Devices 2011-06-21

We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to negative-bias temperature instability (NBTI). The model is suitable application analog circuit design and reproduces results of existing digital-stress NBTI models limit two-level stress signals. It accounts recovery effects during intervals low stress, it predicts stress-pattern dependent saturation degradation at large operation times. Since can be solved numerically an efficient way, we...

10.1109/iirw.2014.7049501 article EN 2014-10-01

We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast measurements an extensive TCAD analysis, we study two physics-based compact models for analog-stress including recovery. The high accuracy both is evidenced single-FET circuit-level ring oscillator experiments. Their numerical efficiency allows direct...

10.1109/ted.2019.2901907 article EN IEEE Transactions on Electron Devices 2019-03-12

Layout generation remains a critical bottleneck in analog circuit design. It is especially distracting when re-using an existing design for similar specification or transferring working to new technology. This paper presents methodology layout of circuits that based on modular and so-called "executable flow description". created once manually allows describe the technology independent parameterizable manner assuring consistent view Complex layouts can be negligible time, achieving early...

10.1109/date.2011.5763267 article EN 2011-03-01

As feature sizes shrink, random fluctuations gain importance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be considered design analysis properly estimate their impact avoid expensive over-design. Statistical MOSFET compact modeling is required accurately capture marginal distributions of varying parameters preserve correlations. Due limited simulator capabilities, variables are often assumed normally distributed. Although...

10.1109/essderc.2011.6044209 article EN 2011-09-01

Process variations increasingly challenge the manufacturability of advanced devices and yield integrated circuits. Technology computer-aided design (TCAD) has potential to make key contributions minimize this problem, by assessing impact certain on device, circuit, system. In way, TCAD can provide information necessary decide investments in processing level or adoption a more variation tolerant process flow, device architecture, circuit chip level. first two consecutive papers, sources state...

10.1109/ted.2011.2150225 article EN IEEE Transactions on Electron Devices 2011-06-21

Process variations and atomic-level fluctuations increasingly pose challenges to the design analysis of integrated circuits by introducing variability. Although several approaches have been proposed deal with inherent statistical nature circuit design, we consider them incomplete two important aspects often being insufficiently addressed: 1) non-Gaussian distributions 2) highly correlated parameters. To address these points, propose a fully multivariate approach based on an arbitrary model....

10.1109/tcad.2015.2459042 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2015-08-24

We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages thus go beyond existing studies for digital stress. As a result, we propose physics-based compact model analog-stress which builds upon extensive TCAD analysis our ultra-short-delay experimental data. The numerical efficiency allows its direct coupling electric circuit simulators permits accurately account already during design. Our enables calculation time-dependent variability...

10.1109/irps.2016.7574540 article EN 2022 IEEE International Reliability Physics Symposium (IRPS) 2016-04-01

Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification robust (pro-active) EM-aware design - where the circuit layout designed with individual EM-robust solutions urgently needed. This tutorial will give an overview of and its effects on present future integrated circuits (ICs). We introduce physical process specific characteristics that can be affected during...

10.1145/3240765.3265971 article EN 2018-11-05

28 nm high-k metal gate CMOS SRAM circuits were subjected to controlled mechanical load by nanoindentation. A thinning procedure down about 35 μm of remaining Si enables high stress fields in the vicinity operational cells which embedded a flip chip package and loads from backside. It was found that loading leads an increase bit cell fail probability around nanoindentation point. The effects are reversible, i.e. failures completely released upon relieve. results attained here provide...

10.1109/irps.2018.8353607 article EN 2022 IEEE International Reliability Physics Symposium (IRPS) 2018-03-01

Variability continues to pose challenges integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions particular problems exist, but they do not allow a common view on performance variability including potentially correlated non-Gaussian parameter distributions. In this paper, we present probabilistic approach for modeling as an alternative: model parameters are treated multi-dimensional random variables. Such fully mul-tivariate description...

10.5555/2616606.2616887 article EN 2014-03-24

We present a BTI compact model that is able to account for the complex stress patterns encountered in electronic circuits. Such are composed of various blocks corresponding different circuit operation states, protocol modes or input conditions, and repeat within composite, hierarchical structure. The work extends previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. provide insight into some principal characteristics degradation under patterns,...

10.1109/iirw.2016.7904888 article EN 2016-01-01

In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change virtual prototype model. The injection is done at beginning of simulation by rewiring involved netlists. During on realtime platform, faults can be activated or deactivated triggered sequences, statistical effects events from real world. some cases even auto-generated directly formal specification, which further automates development process safety-relevant systems....

10.23919/date51398.2021.9474066 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2021-02-01

There is an increasing demand for simulation strategies electro-thermal analysis of electronic systems. In this study cases are investigated, where self induced thermal dynamics influence the electrical behavior device. A method generation models proposed, which requires coarse information on layout while allowing evaluation interactions tentatively. Here, chip divided into a number columns, in lateral gradient temperature considered to be negligible. simple RC-network used model each layer...

10.1109/estc.2010.5642926 article EN 2010-09-01

To verify the reliability of electronic circuits and systems in automotive applications, qualification according to industry-standards, such as AEC-QIOO, is state art. But will it be sufficient for future applications? Simulationbased assessments IC system development are intended complement allow efficient investigations product reliability. Aging simulations analog have been available years, but hardly used. This article discusses degradation models one bottleneck, outlines different...

10.1109/iirw49815.2020.9312870 article EN 2020-10-01

We propose an innovative thermal modeling approach that takes into account different "levels-of-knowledge" as they become available during the design phases of microelectronic systems. There are many tools for simulations which well-suited high-precision modeling. However, their applicability severely diminishes if CAD models not or time is limited. Especially electro-thermal co-design, where several spins between and simulation required, quickly becomes prohibitively large. By a combination...

10.1109/therminic.2013.6675192 article EN 2013-09-01

Variability continues to pose challenges integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions particular problems exist, but they do not allow a common view on performance variability including potentially correlated non-Gaussian parameter distributions. In this paper, we present probabilistic approach for modeling as an alternative: model parameters are treated multi-dimensional random variables. Such fully mul-tivariate description...

10.7873/date2014.243 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2014-01-01

On the example of a 28nm SRAM array, this work presents novel reliability study which takes into account effect externally applied mechanical stress in circuit simulations. This method is able to predict bit failures caused by via piezoresistive effect. The stability each single cell simulated using static noise margin. Finally, whole array's behavior reproduced including device parameter variations Monte-Carlo results show good agreement with corresponding experiments was introduced array...

10.1109/essderc.2018.8486911 article EN 2018-09-01

Variability continues to pose challenges integrated circuit design. With statistical static timing analysis and high-yield estimation methods, solutions particular problems exist, but they do not allow a common view on performance variability including potentially correlated non-Gaussian parameter distributions. In this paper, we present probabilistic approach for modeling as an alternative: model parameters are treated multi-dimensional random variables. Such fully mul-tivariate description...

10.7873/date.2014.243 article EN Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 2014-01-01

For analog and mixed-signal circuit design a modeling methodology is needed which well suited to the requirements of structured synthesis flow. It ensures that intended specification met without over-design. Behavioral models are able provide level knowledge on higher abstraction levels by including non-idealities parasitics from realization, allows realistic comparison different architectures. At same time these fast enough explore space optimize translation with respect system performance...

10.1109/iscas.2006.1692874 article EN 1993 IEEE International Symposium on Circuits and Systems 2006-09-22

In this paper a method for dynamic fault injection and simulation as well its application to MEMS based sensor systems is described. The prerequisite approach the availability of accurate, but likewise numerically efficient models element. Simulations on SystemC AMS are suitable analyze nominal behavior complex including electronics mechanical elements [1], [2]. They offer capabilities represent analog digital hardware software nonelectrical components in one environment. Especially...

10.1109/dtip.2018.8394196 article EN 2018-05-01
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