A5038437884- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Advancements in PLL and VCO Technologies
- Analog and Mixed-Signal Circuit Design
- Advanced Optical Network Technologies
- Smart Grid Energy Management
- Optical Network Technologies
- Energy Efficiency and Management
- Interconnection Networks and Systems
- Radio Frequency Integrated Circuit Design
- Semiconductor Quantum Structures and Devices
- Building Energy and Comfort Optimization
- Integrated Circuits and Semiconductor Failure Analysis
- Microwave Engineering and Waveguides
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Video Coding and Compression Technologies
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Advanced Vision and Imaging
- Radiation Effects in Electronics
- Gait Recognition and Analysis
- Electromagnetic Compatibility and Noise Suppression
- 3D IC and TSV technologies
- Antenna Design and Analysis
Sri Ramachandra Institute of Higher Education and Research
2024
Sri Sivasubramaniya Nadar College of Engineering
2014-2024
ASA College
2017
San Diego State University
2007
University of Delaware
2000-2003
University of North Carolina at Charlotte
1998-2002
Nokia (United States)
2000
Fluctuation and Noise LettersAccepted Papers No AccessA Method to Design Efficient Shaping IIR Filters for Delta-Sigma Modulators using Modified Jacobian Chain FunctionsJ. Arockia Twinkle, R. Srinivasan, Premanand V. ChandramaniJ. Srinivasan Search more papers by this author , Chandramani https://doi.org/10.1142/S0219477525500427Cited by:0 (Source: Crossref) PreviousNext AboutFiguresReferencesRelatedDetailsPDF/EPUB ToolsAdd favoritesDownload CitationsTrack CitationsRecommend Library...
We report the flip-chip bonding of a 16/spl times/16 array 970-nm vertical-cavity surface-emitting lasers (VCSELs) to an silicon CMOS driver circuits. The small-signal bandwidth bonded VCSEL is in excess 4 GHz. Individual VCSELs are capable being modulated by circuits at 1 Gb/s. thermal impedance 1/spl deg/C/mW. measured crosstalk suppression between channels approximately 20 dB. Simultaneous parallel testing up 80 Gb/s per demonstrated.
The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses reflective system to globally interconnect multichip array smart pixel devices. three-dimensional links each chip directly every other with dedicated bidirectional parallel data path. in experiments, several smart-pixel devices were...
We present a device concept based on cascaded electro-optic deflection in domain microengineered ferroelectric chip. In our design, large angles are achieved by cascading several smaller scanners single chip, such that each successive scanner stage builds upon the of previous stage. demonstrate basic using two-stage fabricated crystal wafer LiTaO3. By operating specially designed programmable multichannel driver provides ±1.1 kV per stage, total scan angle 25.4° at 5 kHz was demonstrated....
The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays monolithically integrated vertical-cavity surface-emitting lasers (VCSEL's) photodetectors (PD's) were designed, fabricated, incorporated into a folded system that links 10 cm x multichip smart pixel plane to itself in global point-to-point pattern. effects fully connected network which each chip all...
Abstract Recently, human gait pattern has turned into an essential biometric feature to recognize individual remotely. Gait as a becomes challenging owing variation in appearance under different covariate conditions (eg, shoe, surface, haul, viewpoint and attire). The covariates may alter few fragment of while other stay unaltered, leading lower the probability correct identification. To overcome such variation, improved recognition strategy is proposed this article by energy image...
A 'triggered' transimpedance digital optical receiver is described which usable in noisy environments typical of dense mixed-signal circuits. Results show enhanced immunity to supply variations compared conventional receivers.
This work explores the injection locked single and differential ended ring VCO (Voltage Controlled Oscillator) suitable for a frequency synthesizer to operating over wide range of frequencies with reduced phase noise. Along design, comparisons between 3 stage topologies were studied. Single was observed have tuning 1.2 3.6 GHz noise −110.2 dBc/Hz at 10 MHz offset design 1.5 3.1 −109.9 offset. The VCOs designed using 90 nm CMOS technology in ADS (Advance Design System).
Wide tuning range delay cell based 3-stage differential ring VCO designed using 90nm CMOS process operating at 2.6 GHz frequency shows better single event tolerance compared to diode-connected, triode load and Maneatis topologies. This topology can be used in PLL DLL clock generation applications for improved radiation LET values between 10-50 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg.
This paper proposes a system-on-chip design to perform run-time reconfiguration using soft-core processor. The reconfigurable module consists of set Processing Elements (PEs) that are fully connected each other through crossbar network. Run-time is achieved by dynamically selecting the desired number PEs based on input data dynamic selection leads optimum resource utilization and lesser power consumption for computationally intensive applications such as media processing. Optimization was...
Summary Motion estimation is the important and computationally intensive part of any video encoding. The objective this paper to design analyze coarse fine reconfiguration processing element‐based hardware for block matching–based motion in H.265/HEVC processing. Sum absolute difference (SAD) commonly used criteria matching process. User input taken as parameter reconfiguration, threshold value SAD considered reconfiguration. Processing elements are units designed performing calculation. In...
Day-ahead electricity tariff prediction is advantageous for both consumers and utilities. This article discusses the home energy management (HEM) scheme consisting of an predictor appliance scheduler. The random forest (RF) technique predicts a short-term next 24 hours using past three months information. provides information to schedule appliances at most preferred time slot consumer with minimum tariff, aiming high comfort low bill consumers. proposed approach allows user be aware their...
This paper reports progress toward the experimental demonstration of a smart pixel based optical interconnection prototype currently being developed under Free-space Accelerator for Switching Terabit Networks (FAST-Net) project. The system incorporates 2D arrays monolithically integrated high- bandwidth vertical cavity surface emitting lasers (VCSELs) and photodetectors (PDs). A key aspect FAST-Net concept is that all pixels are distributed across single multi-chip plane. plane connected to...
This article has been retracted. A retraction notice can be found at https://doi.org/10.3233/JIFS-219433.
Highly interconnected multiprocessor systems are now performance limited by the backplane interconnection bottleneck associated with planar technologies. Smart pixel throughput capabilities projected to exceed I Thitls/cm2 [1] and offer promise of overcoming bottlenecks technologies for many types interconnection-limited problems. Systems that use smart pixel-based free space optical interconnects (FSOI) provide two general dense capabilities: intelligent parallel data transfer interchange....
We have flip-chip bonded a 16×16 array of 970nm VCSELs to Silicon CMOS circuit. The device yield after bonding and packaging the Optoelectronic-VLSI chip is approximately 96%. Individual are capable modulated by circuit at IGbit/s. Parallel testing 80VCSELs IGbit/s per VCSEL presented.