A5053364831- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Optical Network Technologies
- Infrared Target Detection Methodologies
- Advanced Optical Network Technologies
- CCD and CMOS Imaging Sensors
- Interconnection Networks and Systems
- Advanced Semiconductor Detectors and Materials
- Semiconductor Quantum Structures and Devices
- Advanced Optical Sensing Technologies
- Optical Systems and Laser Technology
- solar cell performance optimization
- Astronomical Observations and Instrumentation
- Adaptive optics and wavefront sensing
- Advancements in PLL and VCO Technologies
- 3D IC and TSV technologies
- GaN-based semiconductor devices and materials
- Advanced optical system design
- Advanced Photonic Communication Systems
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon and Solar Cell Technologies
- Advanced Memory and Neural Computing
- Embedded Systems and FPGA Design
- Chalcogenide Semiconductor Thin Films
- Parallel Computing and Optimization Techniques
University of Delaware
2013-2024
Chip Design Systems (United States)
2019-2023
University of Iowa
2018
North Carolina State University
1999-2003
University of North Carolina at Charlotte
1993-2002
University of California, San Diego
1988-2000
AT&T (United States)
1995
University of California, Berkeley
1989
Abstract The Very High Efficiency Solar Cell (VHESC) program is developing integrated optical system–PV modules for portable applications that operate at greater than 50% efficiency. We are integrating the design with solar cell design, and have entered previously unoccupied space. Our approach driven by proven quantitative models integration of these designs. Optical systems efficiency an 93% device results under ideal dichroic splitting optics summing to 42·7 ± 2·5% described. Copyright ©...
The advent of optoelectronic computers and highly parallel electronic processors has brought about a need for storage systems with enormous memory capacity bandwidth. These demands cannot be met current technologies (i.e., semiconductor, magnetic, or optical disk) without having the system completely dominate in terms overall cost, power consumption, volume, weight. As solution, we propose an volume based on two-photon effect which allows high density access. In addition, 3-D advantages...
The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared. bases the comparison include speed, bandwidth, power consumption, footprint area. communication network used in is a synchronous packet-switched built from 2*2 bit-serial switching elements. CMOS technology was implementation, it assumed that entire resides on single chip. Regular free-space optical interconnects implementation. results show for large optoelectronics offers higher...
As the use of computers has grown, so too concern about amount power they consume. Data centers, for example, are limited in scalability as struggle with soaring energy costs from many large companies relying on fast, reliable, and round-the-clock computing services. On large-scale clusters, like data even a small drop consumption can have effects. Across contexts, reducing consumed by become major focus. In this paper, we present new approach mapping software design to empirical results...
This paper investigates, at the system level, performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific considered is a packet-switched, free-space shuffle-exchange multistage network (MIN). System bandwidth used as performance measure, while area, power, volume constitute cost measures. A detailed design analysis of two-dimensional (2-D) routing with variable grain size K presented. architecture permits conventional 2...
As the use of computers has grown, so too concern about amount power they consume. Data centers, for example, are limited in scalability as struggle with soaring energy costs from many large companies relying on fast, reliable, and round-the-clock computing services. On large-scale clusters, like data even a small drop consumption can have effects. Across contexts, reducing consumed by become major focus. In this paper, we present new approach mapping software design to empirical results...
Single element 33×33 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> InAs/GaSb superlattice light-emitting diodes (SLEDs) operating at 77 K with peak emission approximately 4.6 are demonstrated. A radiance of 2.2 W/cm /sr was measured corresponding to an apparent temperature greater than 1350 within the 3-5 band. 48 pitch, 512 × individually addressable LED array fabricated from a nominally identical SLED wafer, hybridized read-in...
The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses reflective system to globally interconnect multichip array smart pixel devices. three-dimensional links each chip directly every other with dedicated bidirectional parallel data path. in experiments, several smart-pixel devices were...
This paper introduces programmable arrays of optically inter-connected electronic processors and compares them with conventional symbolic substitution (SS) systems. The comparison is made on the basis computational efficiency, speed, size, energy utilization, programmability, fault tolerance. small grain size space-invariant connections SS lead to poor difficult programming, incorporation Reliance optical gates as its fundamental building elements shown give utilization. Programmable...
ABSTRACT To achieve high energy conversion efficiency, a solar module architecture called lateral spectrum splitting concentrator photovoltaics (LSSCPV) is being developed. LSSCPV can concentrate available sunlight and laterally split single beam into bands with different spectra for absorption by cells band gaps matched to the spectrum. Test assemblies of sample were constructed, each which contains four p–n junctions two optical pieces. Independent experiments or simulations had been...
We present a device concept based on cascaded electro-optic deflection in domain microengineered ferroelectric chip. In our design, large angles are achieved by cascading several smaller scanners single chip, such that each successive scanner stage builds upon the of previous stage. demonstrate basic using two-stage fabricated crystal wafer LiTaO3. By operating specially designed programmable multichannel driver provides ±1.1 kV per stage, total scan angle 25.4° at 5 kHz was demonstrated....
As the use of computers has grown, so too concern about amount power that they consume. Data centers, for example, are limited in scalability as struggle with soaring energy costs many large companies rely on fast, reliable, and round-the-clock computing services. On large-scale clusters, like data even a small drop consumption can have effects. Across contexts, reducing consumed by become major focus. In this paper, we present new approach tool mapping software design to describe how such...
The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays monolithically integrated vertical-cavity surface-emitting lasers (VCSEL's) photodetectors (PD's) were designed, fabricated, incorporated into a folded system that links 10 cm x multichip smart pixel plane to itself in global point-to-point pattern. effects fully connected network which each chip all...
In structured light illumination (SLI), the nonlinear distortion of optical devices dramatically ruins accuracy three-dimensional reconstruction when using only a small number projected patterns. We propose universal algorithm to calibrate these device nonlinearities accurately precompensate Thus, no postprocessing is needed correct for distortions while patterns can be reduced down as few possible. Theoretically, proposed method applied any SLI pattern strategy. Using three-pattern method,...
The demand for high-speed and/or high-temperature infrared (IR) scene projectors has led to the development of systems based on IR light-emitting-diode (LED) arrays. Using mid-wave (3--5 μm) superlattice LED arrays, a 512 × pixel projection system operating at 100 Hz been fully developed. These LEDs, flip-chip bonded read-in integrated circuit, display temperatures up 1350 K when cooled liquid nitrogen temperature (77 K). custom drive electronics and packaging, array nonuniformity corrected...
Very High Efficiency Solar Cell (VHESC) program is developing integrated optical/photovoltaic modules for portable applications that operate at 50 percent efficiency. Test sub-modules incorporating four p-n junctions and corresponding optics have been realized are predicted to realize efficiency greater than 40%. Phased implementation requires measurement inspect accomplished work provide improvement direction the next step. The comparison between real performance of four-junction test...
Loaded and unloaded ring-oscillator circuits with an electrical surface-normal 850 nm optical readout are fabricated using a hybrid 0.8 µm silicon-CMOS/GaAs-AlGaAs MQW process. Measurements of the oscillation frequency these show total capacitance associated flip-chip-bonded modulators as low 52 fF.
The flip chip bonding process is optimized by varying the pressure, temperature, and time. 68times68 mid wave infrared (MWIR) LED array was hybridized onto Si-CMOS driver with same number of pixels. Each pixel has two indium bumps, one for cathode another anode. Both CMOS drivers have 15-mum-square Indium bump contact pads. We used Karl Suss FC150 machine array. From current-voltage characteristics, it concluded that results in uniform very low resistance. electrical optical characteristics...
We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance jitter or skew, spatial format wavelength and independent flow control for the input output channels. It serves as...
We present the first demonstration of a dense VLSI RAM technology with high-speed optical read and write capability. The CMOS-based Static-RAM is capable parallel access read/write speeds limited by native times. fabricated 2/spl times/2 mm optoelectronic-VLSI test chip incorporating 800-b storage 200 I/O based on hybrid integration GaAs-AlGaAs MQW modulators CMOS. Results from photonic-SRAM test-chip confirm 6.2 ns 8-ns
A low-cost, surface-mountable parallel-fiber optical link, which employs passive mechanical alignment of its elements, is described. The links are fabricated as separate transmitter and receiver modules comprised 8 or 12 channels operating at a maximum rate 1.25 GBd per channel. electro-mechanical platform constructed using materials techniques originally developed for fabricating tape ball grid array (TBGA) IC packages. Electrical I/O provided via 6/spl times/10 solder on 50 mil centers....
We present AMOEBA: a single-chip asynchronous multiprocessor optoelectronic bit-sliced arrayed crossbar switch intended to provide switched interconnection between multiple processors in distributed computing environment. AMOEBA relies on optoelectronic-VLSI integration, free-space optical interconnects, and wavelength-and-space-division multiplexed networking single-mode fiber. report the implementation testing of first generation, 16-channel prototype compact opto-mechanical transceiver...
Accelerated bit-error-ratio (BER) measurement techniques using specialized test equipment are widely used for rapidly verifying the low BER (<10/sup -12/) of high-performance optical links. However, once these links deployed in field, it takes days to weeks complete such measurements a conventional testing method. This paper describes an transceiver architecture with on-chip accelerated mechanics that reduces "in field" time minutes. The approach described this uses integrated interference...