A5060594809- Physical Unclonable Functions (PUFs) and Hardware Security
- Integrated Circuits and Semiconductor Failure Analysis
- VLSI and Analog Circuit Testing
- Cryptographic Implementations and Security
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Neuroscience and Neural Engineering
- Embedded Systems Design Techniques
- Coding theory and cryptography
- Advanced Malware Detection Techniques
- Security and Verification in Computing
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Cryptography and Residue Arithmetic
- Quantum Computing Algorithms and Architecture
- Interconnection Networks and Systems
- Quantum-Dot Cellular Automata
- Electrostatic Discharge in Electronics
- VLSI and FPGA Design Techniques
- Cryptography and Data Security
- Parallel Computing and Optimization Techniques
- Chaos-based Image/Signal Encryption
- Advancements in Photolithography Techniques
- Adversarial Robustness in Machine Learning
Tallinn University of Technology
2020-2025
Carnegie Mellon University
2017-2024
University of Bristol
2014-2017
Laboratoire Traitement et Communication de l’Information
2012-2013
Centre National de la Recherche Scientifique
2012-2013
Télécom Paris
2012-2013
Universidade Federal do Rio Grande do Sul
2011-2012
Quantum computers pose a threat to the security of communications over internet. This imminent risk has led standardization cryptographic schemes for protection in post-quantum scenario. We present design methodology future implementations such algorithms. is manifested using NIST selected digital signature scheme CRYSTALS-Dilithium and key encapsulation CRYSTALS-Kyber. A unified architecture, <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Hardware Trojan Horses have emerged as great threats to modern electronic design and manufacturing practices. Because of their inherent surreptitious nature, test vector generation detect hardware horses is a difficult problem. Efficient online detection techniques can be more effective in horses. In this paper, we propose low-overhead technique which inserts malicious logic circuitry at netlist sites chosen by an algorithm that employs intelligent accurate analysis fault propagation through...
Unifying the forward and inverse operations of number theoretic transform (NTT) into a single hardware module is common practice when designing polynomial coefficient multiplier accelerators as used in post-quantum cryptographic algorithms.This work experimentally evaluates that this design unification not always advantageous.In context, we present three NTT architectures: (i) A (FNTT) architecture, (ii) An (INTT) architecture (iii) unified (UNTT) for computing FNTT INTT computations on...
In today's integrated circuit (IC) ecosystem, owning a foundry is not economically viable, and therefore most IC design houses are now working under fabless business model. order to overcome security concerns associated with the outsorcing of fabrication, Split Manufacturing technique was proposed. Manufacturing, Front End Line (FEOL) layers (transistors lower metal layers) fabricated at an untrusted high-end foundry, while Back (BEOL) (higher manufactured trusted low-end foundry. This...
This paper proposes a soft error characterization methodology to analyze multiple faults caused by single-event-induced charge sharing in standard-cell based ASIC designs. Fault injection campaigns have been executed using data provided placement analysis as well pulse width modeling through electrical simulation. Experimental results demonstrate that the rate can be largely overestimated if is not considered.
Globalization of IC manufacturing has led to increased security concerns, notably IP theft. Several logic locking techniques have been developed for protecting designs, but they typically display very large overhead, and are generally susceptible deciphering attacks. In this paper, we propose latch-based locking, which manipulates both the flow data in design. This method converts an interconnected subset existing flip-flops pairs latches with programmable phase. tandem, decoy added,...
Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these by preventing an adversary from fully understanding IC (or parts of it). The use reconfigurable elements inside is a known technique, either coarse grain block (i.e., eFPGA) or fine element FPGA-like look-up tables). This paper presents security-aware CAD...
In this brief, we realize different architectural techniques for improving the performance of post-quantum cryptography (PQC) algorithms when implemented as hardware accelerators on an application-specific integrated circuit (ASIC) platform. Having SABER a case study, designed 256-bit wide architecture geared high-speed cryptographic applications that incorporates smaller and distributed SRAM memory blocks. Moreover, have adapted building blocks to process words. We also used buffering...
Polynomial multiplication is a bottleneck in most of the public-key cryptography protocols, including Elliptic-curve and several post-quantum algorithms presently being studied. In this paper, we present library various large integer polynomial multipliers to be used hardware cryptocores. Our contains both digitized non-digitized multiplier flavours for circuit designers choose from. The supported by C++ generator that automatically produces multipliers' logic Verilog HDL amenable FPGA ASIC...
The integrated circuit (IC) ecosystem, today, is widely distributed. Usually, a handful of companies involved in the development single chip – an environment that presents many opportunities for malicious activities such as insertion hardware trojan horses. This work specialized form able to mount hardware-based ransomware attack, attack previously only existed software domain. therefore termed and main contribution this work. As case studies, two architectures are presented, along with...