Shih-Chang Hung

ORCID: 0000-0002-5860-6713
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About
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Research Areas
  • Radio Frequency Integrated Circuit Design
  • Advanced Power Amplifier Design
  • PAPR reduction in OFDM
  • Microwave Engineering and Waveguides
  • Advancements in PLL and VCO Technologies
  • EEG and Brain-Computer Interfaces
  • Energy Efficient Wireless Sensor Networks
  • Advanced Sensor and Energy Harvesting Materials
  • Millimeter-Wave Propagation and Modeling

Michigan State University
2018-2022

Carnegie Mellon University
2011-2017

A 30.1-dBm quadrature transmitter is implemented based on Class-G IQ-cell-shared switched-capacitor power amplifier (SCPA) and voltage mismatch compensation techniques for dual-supply in a SCPA. For the operation SCPA, merged cell switching (MCS) technique comprising vector amplitude (VAS) phase (VPS) proposed. The VAS boosts system efficiency (SE) by enabling with multiple supply voltages VPS conserves information cells that process vectors. linearization SCPA minimizes distortion arises...

10.1109/jssc.2019.2904209 article EN IEEE Journal of Solid-State Circuits 2019-04-26

This article presents an efficient quadrature digital power amplifier (DPA) based on a complex-domain Doherty (CDD) architecture. The proposed CDD architecture allows PA to achieve high efficiency through operation in complex domain using two independent vectors with different amplitudes and phases. It demonstrates when have in-phase components the by introducing additional peak. DPA switch-capacitor (SCPA) employs dual-supply Class-G techniques enhance system (SE) adds three peaks down...

10.1109/jssc.2020.3040973 article EN IEEE Journal of Solid-State Circuits 2020-12-10

A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, time interleaving (TI). The demonstrates six efficiency peaks seamless curves between the in back-off (PBO) region with three efficiencyenhancement techniques. For implementation of efficient linear Class-G technique, single-supply current-reuse switch proposed. It realizes operation without any additional dedicated...

10.1109/jssc.2020.3022012 article EN IEEE Journal of Solid-State Circuits 2020-09-18

An efficient digital quadrature power amplifier is presented. It shows a good system efficiency (SE) at back-off, demonstrating four peaks with the combination of dual-supply Class-G and complex-domain Doherty (CDD) in IQ plane. The proposed transmitter 65-nm CMOS demonstrates 27.8-dBm peak output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) SE 32.1%. For an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal 13.1-dB (12.4-dB)...

10.1109/rfic.2019.8701789 article EN 2019-06-01

A quadrature Class-G switched-capacitor power amplifier (SCPA) is implemented with a merged cell switching (MCS) and an inherent mismatch compensation for dual-supply voltage. The MCS technique improves added efficiency (PAE) by adopting operation in IQ-Cell shared SCPA architecture efficient manner. can minimize nonlinearity from the mismatches multiple supply voltages. achieves peak output PAE of 30.1dBm 37.0%, respectively. For 802.11g 64-QAM OFDM signal 10.6dB PAPR (20MHz single-carrier...

10.1109/rfic.2018.8428956 article EN 2018-06-01

In this paper, we present a linear, balanced, fully differential PA with seamless efficiency peaks at 2.5, 6, 8.5, 12, and 18dB PB0s. It leverages combination of the Class-G Doherty techniques further augmentation PBO down to utilizing time-interleaving (Ti) approach (Fig. 24.4.1). At its core, it adopts switched-capacitor (SCPA) for high -efficiency precision bits-to-RF conversion [1-6]. Furthermore, linearity overhead Class -G system is addressed current-reuse, single supply architecture.

10.1109/isscc19947.2020.9063069 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2020-02-01

Digital transmitters (DTX) or digital power amplifiers (DPA) based on RF digital-to-analog converters (DAC) are optimal for wireless in CMOS due to the small chip area, low consumption, and ability evolve with scaling of transistor feature size. A DTX integrates all functions a conventional transmitter into single RFDAC that directly converts bits signals (Fig. 10.7.1) [1]-[3]. It consists circuits (e.g., switches, logic gates, etc.) passive devices rather than traditional mixed-signal,...

10.1109/isscc19947.2020.9063070 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2020-02-01

This study presents a prototype design of an ultra-miniature, wireless, battery-less, and implantable temperature-sensor, with applications to thermal medicine such as cryosurgery, hyperthermia, ablation. The aims at sensory device smaller than 1.5 mm in diameter 3 length, enable minimally invasive deployment through hypodermic needle. While the new may be used for local temperature monitoring, simultaneous data collection from array sensors can reconstruct 3D field treated area, offering...

10.1117/12.874729 article EN Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE 2011-02-06

An 18–50 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The employs a differential quadrature coupler to split received signal into I/Q and provide broadband input match, two-phase double balanced passive mixer downconvert the signal, low-power inverter based LO driver with series resonance peaking flatten gain across frequency baseband LNA 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order Sallen-Key low pass...

10.1109/ims37962.2022.9865519 article EN 2022 IEEE/MTT-S International Microwave Symposium - IMS 2022 2022-06-19

This paper presents a four-channel baseband channel emulator for multi-antenna millimeter-wave system characterization. The is fabricated in 65 nm CMOS and occupies 1.45 mm × 1.2 mm. It comprises an array of four semidigital FIR filters each with 40 complex-valued taps (or 80 real coefficients). supports upto 2Gb/s QPSK, 6bit resolution coefficient maximum power consumption 279 mW.

10.1109/iscas.2017.8050472 article EN 2022 IEEE International Symposium on Circuits and Systems (ISCAS) 2017-05-01

An ultra-wideband 18–50 GHz millimeter-wave (mm-wave) transmitter is presented. The proposed mm-wave designed for compact size and low-power consumption, it suitable an element-level digital phased array system. fully-integrated includes buffers, cascaded baseband amplifiers with sharp roll-off, a local oscillator (LO) driver, broadband coupled line coupler, stacked active mixer fabricated in 45-nm SOI CMOS process. Sallen-Key filters are implemented to provide roll-off remove the aliasing...

10.1109/past49659.2022.9975058 article EN 2022 IEEE International Symposium on Phased Array Systems &amp; Technology (PAST) 2022-10-11
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