A5043660353- Radio Frequency Integrated Circuit Design
- Advanced Power Amplifier Design
- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- PAPR reduction in OFDM
- Low-power high-performance VLSI design
- Wireless Power Transfer Systems
- Microwave Engineering and Waveguides
- Millimeter-Wave Propagation and Modeling
- Advanced MIMO Systems Optimization
- CCD and CMOS Imaging Sensors
- Advancements in PLL and VCO Technologies
- GaN-based semiconductor devices and materials
- Energy Harvesting in Wireless Networks
- Advanced Wireless Communication Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Wireless Body Area Networks
- Antenna Design and Analysis
- Microwave Imaging and Scattering Analysis
- Photonic and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Wireless Networks and Protocols
- Non-Invasive Vital Sign Monitoring
Samsung (South Korea)
2003-2024
Pohang University of Science and Technology
2023
Michigan State University
2018-2022
Qualcomm (United Kingdom)
2013
University of Washington
2009-2012
Qualcomm (United States)
2012
Seattle University
2011
Sogang University
2000-2004
A fully integrated switched-capacitor power amplifier (SCPA) utilizes techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant modulated signal as RF-DAC order to amplify efficiently. The measured maximum output and PAE are 25.2 dBm 45%, respectively. When amplifying 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, error vector magnitude is 2.6% average power-added efficiencies 17.7 27%,
A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. novel voltage-tolerant switch enables the use of two supply voltages which increases efficiency output simultaneously. Envelope digital-to-analog conversion in polar transmitter achieved using SC RF DAC exhibits high at typical backoff levels. In addition, linearity no digital predistortion required. Implemented 65 nm CMOS, measured peak power-added (PAE)...
A 30.1-dBm quadrature transmitter is implemented based on Class-G IQ-cell-shared switched-capacitor power amplifier (SCPA) and voltage mismatch compensation techniques for dual-supply in a SCPA. For the operation SCPA, merged cell switching (MCS) technique comprising vector amplitude (VAS) phase (VPS) proposed. The VAS boosts system efficiency (SE) by enabling with multiple supply voltages VPS conserves information cells that process vectors. linearization SCPA minimizes distortion arises...
This paper introduces an EER 90 nm CMOS experimental prototype switched capacitor power amplifier (SCPA) that achieves high output power, efficiency and linear output-power control using a switched-capacitor-based switching PA without the use of supply modulator. While amplifying 64-QAM OFDM modulation with 20 MHz signal bandwidth it average 17.7 dBm, PAE 32.1%, EVM 2.9%.
This article presents an efficient quadrature digital power amplifier (DPA) based on a complex-domain Doherty (CDD) architecture. The proposed CDD architecture allows PA to achieve high efficiency through operation in complex domain using two independent vectors with different amplitudes and phases. It demonstrates when have in-phase components the by introducing additional peak. DPA switch-capacitor (SCPA) employs dual-supply Class-G techniques enhance system (SE) adds three peaks down...
This work describes a 10-b 150-MSample/s 4-b-per-stage single-channel CMOS pipelined ADC incorporating improved gate-bootstrapping techniques for wideband SHA and temperature- supply-insensitive references. The proposed is designed fabricated in 0.18-/spl mu/m one-poly six-metal technology. measured differential integral nonlinearities are within 0.69 LSB 1.50 LSB, respectively. prototype shows peak signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. maintains the SNDR...
This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves signal processing speed and resolution of ADC by reducing required number unit capacitors half in comparison to conventional ADC. based on can be extended further employing commutated feedback-capacitor (CFCS) prototype achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120...
A digitally-controlled switched-capacitor RF power amplifier (SCPA) is implemented with a transformer-based power-combiner in 90nm CMOS. The individual SCPA cores can be controlled to provide high average output and linearity an "all-switching" mode or increased dynamic range "sequential-switching" mode. delivers peak (average) of 27.0 (20.3) dBm PAE 26% (15.1%) for 64 QAM OFDM modulated signal measured EVM 3.8% the 2.4 GHz band.
A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, time interleaving (TI). The demonstrates six efficiency peaks seamless curves between the in back-off (PBO) region with three efficiencyenhancement techniques. For implementation of efficient linear Class-G technique, single-supply current-reuse switch proposed. It realizes operation without any additional dedicated...
An efficient digital quadrature power amplifier is presented. It shows a good system efficiency (SE) at back-off, demonstrating four peaks with the combination of dual-supply Class-G and complex-domain Doherty (CDD) in IQ plane. The proposed transmitter 65-nm CMOS demonstrates 27.8-dBm peak output (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) SE 32.1%. For an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal 13.1-dB (12.4-dB)...
A 10 b multibit-per-stage pipelined ADC incorporating the merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 68 SFDR for input frequencies up to Nyquist 100 MSample/s. The measured DNL INL are /spl plusmn/0.40 LSB plusmn/0.48 LSB, respectively. fabricated in a 0.25 mu/m CMOS process, occupies 3.6 mm/sup 2/ active die area consumes 208 mW under 2.5 V power supply.
The Wi-Fi 7 standard (IEEE 802.11be) was developed to meet the growing need for increased capacity and high throughput. However, new, more demanding requirements RF/analog circuits, including an extended bandwidth of 320MHz with 4K-QAM, result in complexity circuit design address issues linearity, noise, bandwidth, power consumption. Despite these challenges, promises faster reliable wireless connectivity. This paper presents a transceiver that demonstrates excellent linearity smallest...
A digital power amplifier (DPA) that uses switched-capacitor circuits in 90 nm CMOS to efficiently amplify signals with large peak-toaverage ratios is described this article. In traditional DPAs, a code word representing desired output envelope voltage used control combination of wide-dynamic range current sources. contrast, the (SCPA) provides linear characteristic by using selectively switch or not bank integrated capacitors at RF carrier frequency. Therefore, SCPA combines functionalities...
A digitally-controlled switched-capacitor RF power amplifier (SCPA) that uses a dual-supply voltage, class-G architecture is implemented in 65nm CMOS. It implements signal envelope digital-to-analog conversion using switching functions controlled by digital logic to achieve superior efficiency and linearity at output backoff. The SCPA delivers peak (average) of 24.3 (16.8) dBm with PAE 44% (33%) for an IEEE 802.11g (64 QAM OFDM) measured EVM 2.9 % the 2.4 GHz band. No predistortion was...
A quadrature Class-G switched-capacitor power amplifier (SCPA) is implemented with a merged cell switching (MCS) and an inherent mismatch compensation for dual-supply voltage. The MCS technique improves added efficiency (PAE) by adopting operation in IQ-Cell shared SCPA architecture efficient manner. can minimize nonlinearity from the mismatches multiple supply voltages. achieves peak output PAE of 30.1dBm 37.0%, respectively. For 802.11g 64-QAM OFDM signal 10.6dB PAPR (20MHz single-carrier...
In this paper, we present a linear, balanced, fully differential PA with seamless efficiency peaks at 2.5, 6, 8.5, 12, and 18dB PB0s. It leverages combination of the Class-G Doherty techniques further augmentation PBO down to utilizing time-interleaving (Ti) approach (Fig. 24.4.1). At its core, it adopts switched-capacitor (SCPA) for high -efficiency precision bits-to-RF conversion [1-6]. Furthermore, linearity overhead Class -G system is addressed current-reuse, single supply architecture.
Digital transmitters (DTX) or digital power amplifiers (DPA) based on RF digital-to-analog converters (DAC) are optimal for wireless in CMOS due to the small chip area, low consumption, and ability evolve with scaling of transistor feature size. A DTX integrates all functions a conventional transmitter into single RFDAC that directly converts bits signals (Fig. 10.7.1) [1]-[3]. It consists circuits (e.g., switches, logic gates, etc.) passive devices rather than traditional mixed-signal,...
A 10b 50MS/s pipelined ADC, implemented in a 0.13μm CMOS process, consumes of 15mW and occupies an active die area 0.2mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2 </sup> . In the prototype high-to-low analog level-shifting SHA is proposed to deal with wide input range 2V <sub xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> differential. PVT-insensitive bias generator employed for low voltage operation. The measured DNL INL are...
This letter presents the first demonstration of 5G millimeter-wave hybrid front-ends (FEs) for a phased-array transceiver in order to show efficient transmitter performance with low cost and compact area. The configuration proposed FEs is CMOS-based combined GaAs HEMT-based power-cell array obtain all benefits silicon III-V technology. architecture design method (TX)/receiver (RX) combiner antenna-port sharing suitable structure newly introduced. A developed 29-GHz FE achieves linear output...
As mobile applications have become more prevalent, the demand for higher network capacity and data rates has increased. This led to development of complicated platforms including RF transceivers that can support various frequency bands, a massive multiple-input multiple-output (MIMO), multiple carrier components (CCs) aggregations (CAs). paper presents fully integrated, versatile transceiver designed handle high achieve cost-efficient solution, incorporating techniques. The comprises 24...
A 10 b 150 MHz multi-bit-per-stage single-channel CMOS pipelined ADC, incorporating temperature- and supply-insensitive references improved gate-bootstrapping techniques for a wideband SHA, achieves SNDR of 52 dB SFDR 65 at MS/s. The fabricated in 0.18 /spl mu/m CMOS, occupies an active die area 2.2 mm/sup 2/ consumes 123 mW 1.8 V.
This brief presents a hybrid oscillator architecture that combines an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> resonator and inverter-based ring to exploit the inherent benefit of for frequency accuracy with low power consumption. uses period as reference time control through feedback loop. By intermittently turning on error detection, its consumption could be...