This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic margin metrics. Reliability has become a major concern designs modern technologies. Both local mismatch VDD degrade read stability ability. Several approaches, including traditional SNM, BL margin, N-curve method, can be used to measure margin. However, approaches cannot indicate impact of dependencies cell stability. We propose analyze by considering...

The growth of battery-powered mobile and wearable devices has increased the importance low-power operation cost in system-on-a-chip (SoC) design. Supply-voltage scaling is predominant approach to active power reduction for SoC design, including voltage on-die memory given increasing levels integration. SRAM can limit minimum operating (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</inf> ) a often leading introduction separate supplies...

A 0.6-1.1 V, 84 Mb pipelined SRAM array design implemented in 14 nm FinFET CMOS technology is presented. Two architectures featuring a high-density 0.0500 μm 2 6T bitcell and 0.0588 targeting low voltage operation are detailed. The reaches 2.7 GHz at 1.1 V with 14.5 Mb/mm bit density, while the optimized can operate 0.6 1.5 under typical process conditions. capacitive charge-share transient collapse write-assist circuit (CS-TVC) enables 24% reduction write energy compared to previous...

Multiported high-performance on-die memories occupy significantly more die area than a comparable single-port memory. Among various multiport memory topologies, the 1-read (R), 1-write (W) 8-transistor (T) Static Random Access Memory (SRAM) with decoupled read port allows separate optimization of and write ports when organized without interleaved logical columns. This enables lower minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

Conventional 6-transistor (6T) SRAM scaling to newer technologies and lower supply voltages is difficult due a complex trade-off space involving stability, performance, power, area. Local global variation make design even more challenging. We present 5-transistor (5T) bitcell that uses sizing asymmetry improve read stability provide an efficient knob for trading off the aforementioned metrics. In this paper, we compare 5T with conventional 6T 8T show how it can be flexible, intermediate...

This paper describes a 5-transistor (5T) SRAM bitcell that uses novel asymmetric sizing approach to achieve increased read stability. Measurements of 32 kb 5 T in 45 nm bulk CMOS technology validate the design, showing functionality below 0.5 V. The has lower write margin than 6 T, but measurements array confirm assist method restores comparable writability with down 0.7

A 23.6-Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a 20.4-Mb/mm SRAM arrays are manufactured in 10-nm FinFET CMOS technology, utilizing high-density 0.0312 μm low-voltage 0.0367 6T bitcells. pulsed-pMOS transient voltage collapse (PP-TVC) write assist circuit is implemented to minimize energy overhead of the TVC technique, delivering 43% reduction compared conventional strong-bias nMOS (SBN-TVC). PP-TVC also achieves up...

The emergence of cloud computing and big data analytics, accompanied by a sustained growth battery-powered mobile devices, continues to drive the importance energy area efficient CPU SoC designs. Low-voltage operation remains one primary approaches for active power reduction, but SRAM l/ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> can limit minimum operating voltage. Device size quantization be challenge compact 6T design in FinFET...

We propose a novel method that exploits BTI to partially offset variation and thus improve SRAM Vmin yield. show correlation between bitcell's power-up state its static noise margin. By applying stress with periodic re-power-up, device mismatch can be compensated by induced changes. The proposed has no extra design area cost. It applied during burn-in test manufacturing and/or used the lifetime of chip from real-time aging hence continue margins. Simulations in 45nm write, read, hold at 6σ...

This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write (WNM) for the same area as a conventional symmetric 6T. improvement is achieved using single V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , without employing assist techniques require multiple voltages. The in noise margins significantly low-voltage robustness consequently minimum operating voltage of (V...

Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive node. Large scale 6T SRAM arrays beyond 65 nm will increasingly rely on assist methods overcome the functional limitations imposed by variation, reduced overdrive inherent read stability/write margin trade off. Factors such as reliability, leakage data retention establish boundary conditions for maximum voltage bias permitted a given circuit...

System-on-Chip (SoC) designs contain a variety of IP blocks which use multiport memories to improve performance by enabling multiple simultaneous operations in the same memory bank. Conventional 2-read/write 8T dual-port SRAMs (2RW) suffer from read and write disturb issues when both wordlines one row are activated at time. 1-read, 1-write decoupled dual port cells (1R1W) eliminate preventing charge-sharing with internal storage nodes while wordline (RDWL) is activated. Dummy-read can also...

Dynamic stability analysis for SRAM has been growing in importance with technology scaling. This paper analyzes dynamic writability designing low voltage nanoscale technologies. We propose a definition write limited V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> . To the best of our knowledge, this is first based on stability. show how affected by array capacity, scaling word-line pulse, bitcell parasitics, and number cycles prior...

SRAM design in scaled technologies requires knowledge of phenomena at the process, circuit, and architecture level. Decisions made various levels hierarchy affect global figures merit (FoMs) an SRAM, such as, performance, power, area, yield. However, lack a quick mechanism to understand impact changes on FoMs makes accurate assessment innovations difficult. Thus, we introduce Virtual Prototyper (ViPro), tool that helps designers explore large space by rapidly generating optimized virtual...

A designer's intent and knowledge about the critical issues trade-offs underlying a custom circuit design are implicit in simulations she sets up for creation verification. However, this is tightly conjoined with technology-specific features decoupled from final schematic traditional flows. As result, easily lost when technology specifics change. This paper presents agnostic simulation environment (TASE), which tool that uses templates to capture separate it components of simulation. TASE...

Exceptionally low minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ) SRAM arrays have been demonstrated on 22nm FinFET power technology (22FFL) [1]. By optimizing an undoped transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> high-density bitcell (HDC) 32Mb 0.107μm high-current (HCC) achieve the 95...

Conventional strobed sense amplifiers (SA) have a fixed offset that dictates the minimum BL droop required during memory read. is major component of read delay and energy. In this paper we propose novel non-strobed sensing scheme can tradeoff with SA delay, allowing to operate lower droop, thus We demonstrate on an 16KB SRAM. Lower swing results in 15% energy per operation. The performance penalty due higher avoided by pipelining into next clock cycle. Thus, addition read, pipelined SRAM 52%...