A5041500446- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- Copper Interconnects and Reliability
- Semiconductor materials and interfaces
- Nanowire Synthesis and Applications
- Advanced Memory and Neural Computing
- 3D IC and TSV technologies
Intel (United States)
2009-2023
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
Two key process features that are used to make 45 nm generation metal gate + high-k dielectric CMOS transistors highlighted in this paper. The first feature is the integration of stress-enhancement techniques with dual metal-gate transistors. second extension 193 dry lithography technology node pitches. Use these has enabled industry-leading transistor performance and high volume technology.
In this paper, Bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps large amount of hysteresis that was consistent literature. The optimized final process demonstrated NMOS PMOS BTI HK+MG are better than SiON at matched E-fields comparable targeted 30% higher use fields. also showed no due to...
A device architecture with n-MOS and p-MOS transistors stacked on top of each other is considered a key option to continue scaling in the semiconductor industry. We report experimental demonstrations gate-all-around based 3D CMOS devices at scaled gate pitch down 60nm. Our most consist 3 nanoribbons 30nm vertical separation, vertically dual-source/drain epitaxy dual metal workfunction stacks. In addition, we demonstrate nanoribbon depopulation process, potentially enabling implementation...
A 23.6-Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a 20.4-Mb/mm SRAM arrays are manufactured in 10-nm FinFET CMOS technology, utilizing high-density 0.0312 μm low-voltage 0.0367 6T bitcells. pulsed-pMOS transient voltage collapse (PP-TVC) write assist circuit is implemented to minimize energy overhead of the TVC technique, delivering 43% reduction compared conventional strong-bias nMOS (SBN-TVC). PP-TVC also achieves up...
In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent and SILC degradation mechanisms have been identified are attributed gate substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes structures at 30% higher E-fields than SiON with a reduction in growth. Extensive long-term stress data collection change voltage acceleration reported.
The emergence of cloud computing and big data analytics, accompanied by a sustained growth battery-powered mobile devices, continues to drive the importance energy area efficient CPU SoC designs. Low-voltage operation remains one primary approaches for active power reduction, but SRAM l/ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> can limit minimum operating voltage. Device size quantization be challenge compact 6T design in FinFET...
Stress induced leakage current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation correlation to SILC increase such gate stack is a result of large trap generations in the bulk-HK. This poses long term reliability concern product standby power can limit operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that The transistor level data, model burn-in stress data support this. With no impact products...
A 21-Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM design using 0.0367-um HCC bitcell on a 10-nm CMOS technology is presented. Gate-modulated selfcollapse (GSC) write-assist utilized to enable 175 mV VMIN reduction with negligible active energy overhead, and modest 5.5% array area overhead 256-Kb instance. Compared NBL TVC techniques, GSC delivers comparable improvement across wide frequency range 31%-108% write reduction.
The recent report of a high-yielding process with Back-Side Power Delivery (BSPD) using PowerVia, the benefits obtained on an Intel E-core implementation, and imminent deployment PowerVia in High- Volume Manufacturing (HVM), are driving rapid expansion R&D across Si Industry to enable future deployments this seminal innovation. One such example is experimental demonstration back-side contacts (BSCONs), which bring about performance scaling benefits. In paper, we will identify discuss...
A 21Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAM design using 0.0367um HCC bitcell on a 10nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write assist utilized to enable 175mV reduction in V <sub xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> with minimal energy overhead. Instance area overhead limited 3-5% by implementing the GSC circuitry row-based configuration modified bitcells.
Exceptionally low minimum operating voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ) SRAM arrays have been demonstrated on 22nm FinFET power technology (22FFL) [1]. By optimizing an undoped transistor and applying industry standard write assist techniques, 16Mb array of 0.087μm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> high-density bitcell (HDC) 32Mb 0.107μm high-current (HCC) achieve the 95...