A5030114105- Advancements in Semiconductor Devices and Circuit Design
- Quantum and electron transport phenomena
- Semiconductor materials and devices
- Advanced Sensor and Energy Harvesting Materials
- Conducting polymers and applications
- Semiconductor Quantum Structures and Devices
- Advanced Memory and Neural Computing
- 3D IC and TSV technologies
- Innovative Energy Harvesting Technologies
- Ferroelectric and Negative Capacitance Devices
- Copper Interconnects and Reliability
- Neuroscience and Neural Engineering
- Physical Unclonable Functions (PUFs) and Hardware Security
- Quantum Computing Algorithms and Architecture
- Thin-Film Transistor Technologies
- Advanced Materials and Mechanics
- Quantum Information and Cryptography
- Quantum optics and atomic interactions
- Integrated Circuits and Semiconductor Failure Analysis
- Radio Frequency Integrated Circuit Design
- Magnetic Field Sensors Techniques
- Modular Robots and Swarm Intelligence
- Tactile and Sensory Interactions
- Synthesis and properties of polymers
University of Basel
2024
UNSW Sydney
2021-2024
Korea Advanced Institute of Science and Technology
2016-2019
Daejeon University
2018
Government of the Republic of Korea
2018
Intel (United States)
2015-2016
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three interconnect layers is described. For high density, a novel self-aligned contact over active gate process elimination of the dummy cell boundaries are introduced. The feature rectangular fins 7nm fin width 46nm height, 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A 32 nm generation logic technology is described incorporating 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation high-k + metal-gate technology, 193 immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT gate dielectric, dual band-edge workfunction metal gates, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> strained silicon, resulting in the...
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on product in high volume, multiple (M4 M6) incorporate an air gap integration scheme to deliver up 17% RC benefit. Pitch Division patterning is introduced yield capable interconnect with minimum pitch of 52nm.
Hole spins are highly promising for spin-qubit technology due to the ability electrically manipulate hole $g$ tensor. However, gaps remain in our understanding of mechanisms that couple electric fields. Here, authors investigate effect unintentional strain on spin state a single confined metal-oxide-semiconductor (MOS) quantum dot. Results show metal electrodes produce nonuniform profile, resulting nanometer-scale variations heavy-hole--light-hole splitting. Therefore, local fields can be...
Abstract Fabric‐based electronic textiles (e‐textiles) have been investigated for the fabrication of high‐performance wearable devices with good durability. Current e‐textile technology is limited by not only delicate characteristics materials used but also fabric substrates, which impose constraints on process. A polydopamine (PDA)‐intercalated memory (PiFAM) a resistive random access (RRAM) architecture reported fabric‐based devices, as step towards promising neuromorphic beyond most...
Holes in silicon quantum dots are promising for spin qubit applications due to the strong intrinsic spin-orbit coupling. The coupling produces complex hole-spin dynamics, providing opportunities further optimise qubits. Here, we demonstrate a singlet-triplet using hole states planar metal-oxide-semiconductor double dot. We rapid control with oscillations up 400 MHz. exhibits coherence, maximum dephasing time of 600 ns, which is enhanced 1.3 μs refocusing techniques. investigate magnetic...
Interconnect process features are described for a 32 nm high performance logic technology. Lower-k, yet highly manufacturable, carbon-doped oxide (CDO) dielectric layers introduced on this technology at three to address the demand ever lower metal line capacitance. The pitches have been aggressively scaled meet expectation density, and resistance electromigration carefully balanced reliability requirements while maintaining lowest possible resistance. A new patterning scheme has used limit...
A new form of generator known as the triboelectric nanogenerator (TENG) has recently been suggested a simple and low-cost solution to scavenge ambient mechanical energy. Although there have substantial advances in TENGs over past few years, power efficiency must be enhanced further before they can practically applied. In present study, we report ferromagnetic nanoparticle-embedded hybrid (FHNG) which operates based on both triboelectricity electromagnetic induction. TENG an (EMG) efficiently...
Holes in silicon quantum dots are receiving attention due to their potential as fast, tunable, and scalable qubits semiconductor circuits. Despite this, challenges remain this material system including difficulties using charge sensing determine the number of holes a dot, controlling coupling between adjacent dots. We address these problems by fabricating an ambipolar complementary metal-oxide-semiconductor (CMOS) device multilayer palladium gates. The consists electron sensor hole double...
We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack introduce the SOC family of interconnects. Enhancement includes improved RC intrinsic capacitance for metal layers over a range process versions stacks offered optimal cost density targeted various applications.
Abstract A nano‐electromechanical (NEM) switch using multilevel states based on the high security physical unclonable function (PUF) is proposed and experimentally demonstrated. Using asymmetric random stiction of a silicon nanowire (SiNW), conventional binary state simply expanded to quaternary‐state encryption key without increasing chip area. The multiple are determined by asymmetrically bent direction SiNW. experimental results show that fabricated NEM‐PUF with multistates retains...
The single-transistor latch in vertical pillar-type FETs with asymmetric source and drain (S/D) was investigated for capacitorless one transistor dynamic random access memory (1T-DRAM). S/D is produced by the different energies of ion implantation at depths pillar. window voltage (Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> ), which difference between latch-up (...
Microwave-induced thermal curing is demonstrated to improve the reliability and prolong lifetime of chips containing nanoscale electron devices. A film graphite powder with high microwave absorbing efficiency was fabricated at low cost. The flexible, bendable, foldable, attachable a chip. commercial off-the-shelf chip representative 3-dimensional (3D) metal-oxide-semiconductor field-effect transistor (MOSFET), known as FinFET, were utilized verify behaviors microwave-induced heat treatment....
<title>Abstract</title> Developing a full-scale quantum computer will require technology platform that allows effective control over individual qubits and their coupling, while also enabling the ability to scale many millions of qubits. Tremendous progress has been made using silicon-based qubits<sup>1–9</sup>, which offer high accuracy qubit operations flexible couplings. However, most advanced silicon incorporate microwave antennae<sup>10</sup> or micromagnets<sup>11</sup> for control....
In this work, we probe the sensitivity of hole-spin properties to hole occupation number in a planar silicon double-quantum dot device fabricated on 300 mm integrated platform. Using DC transport measurements, investigate g-tensor and spin-relaxation induced leakage current within Pauli spin-blockade regime as function magnetic-field orientation at three different numbers. We find spin-leakage be highly anisotropic due light-hole/heavy-hole mixing spin-orbit mixing, but discover anisotropies...
An electron confined by a semiconductor quantum dot (QD) can be displaced changes in occupations of surrounding QDs owing to the Coulomb interaction. For single-spin qubit an inhomogeneous magnetic field, such displacement host results energy shift which must handled carefully for high-fidelity operations. Here we spectroscopically investigate induced charge nearby silicon magnetic-field gradient. Between two different configurations adjacent double QD, spin shows about 4 MHz, necessitates...
A thickness effect of a tribo-dielectric layer (TDL) made ultra-thin polymer in triboelectric energy harvester (TEH) is experimentally and comprehensively studied. The TDL was deposited by the initiated chemical vapor deposition (i-CVD) method its precisely controlled to analyze effect. correlation between output performance determined analytically understood with aid dynamic contact-separation model. In contrast conventional static model, this case increases as owing behavior electron,...
Holes in silicon quantum dots are promising for spin qubit applications due to the strong intrinsic spin-orbit coupling. The coupling produces complex hole-spin dynamics, providing opportunities further optimize qubits. Here, we demonstrate a singlet-triplet using hole states planar metal-oxide-semiconductor double dot. We observe rapid control with oscillations up 400 MHz. exhibits coherence, maximum dephasing time of 600 ns, which is enhanced 1.3 us refocusing techniques. investigate...
In article number 1803825, Yang-Kyu Choi and co-workers demonstrate a nano-electromechanical (NEM) switch by use of the physical unclonable function (PUF) for high security. This PUF is based on inherent random stiction arising from microfabrication. To improve security level, single NEM has more than 4-states, which are distinguished magnitude direction read current. key robustness against microwaves, radiation thermal stress, hence can provide reliable authorized anti-hacking.