A5033588917- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and Analog Circuit Testing
- Graphene research and applications
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Radiation Effects in Electronics
- Molecular Junctions and Nanostructures
- Advancements in Battery Materials
- Advanced machining processes and optimization
- Carbon Nanotubes in Composites
- Solar Radiation and Photovoltaics
- Network Packet Processing and Optimization
- 3D IC and TSV technologies
- Photovoltaic System Optimization Techniques
- Semiconductor materials and interfaces
- Nanowire Synthesis and Applications
- Advanced MEMS and NEMS Technologies
- solar cell performance optimization
- Nanotechnology research and applications
- Advanced Machining and Optimization Techniques
- Advanced Sensor and Energy Harvesting Materials
- Material Dynamics and Properties
Intel (United States)
2023
Maulana Azad National Institute of Technology
2016-2020
IBM (United States)
2008
Poughkeepsie Public Library District
2002-2007
Texas Instruments (United States)
1993
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
A fully functional read and half select disturb-free 1.2 Mb SRAM is demonstrated. Measured results show an operating range of 0.4V to 1.5V -25°C 100°C, speed 6.6+ GHz at IV, 25°C yield 90-100%.
We propose a single-ended disturb-free carbon nanotube field effect transistor (CNFET) based stable nine transistors (9T) SRAM cell using multi-threshold (multi-Vt) technology. Simulations of the CNFET 9T cell, HSPICE model, have shown advantages over conventional Si-CMOS in terms leakage power consumption, dynamic stability, and delay. Due to higher carrier mobility high ION/IOFF ratio makes devices suitable for high-speed nanoelectronics applications. The architecture bit interleaving...
Abstract In this paper, we propose a new design of high‐performance ultralow power carbon nanotube field effect transistor (CNTFET)‐based nine‐transistor static random access memory (SRAM) cell and its implementation using shared bitline (BL) half‐select free techniques. Simulations the 9T SRAM design, CNTFET compact model, have presented merits over silicon‐complementary‐metal oxide semiconductor (CMOS) in terms leakage current, consumption, stability. Uses technique eliminate conflict...
PowerVia increases the efficiency of power delivery by adding back-side interconnects [1]. It also improves performance relaxing minimum front-side interconnect pitch and optimizing them for signaling. Research to further improve density synergistically with includes device contacts stacking. In this paper, we present an experimental demonstration a novel cell architecture back side delivery. Keywords: delivery, contacts, BSCON.
Abstract The entanglement length plays a key role in deciding many important properties of thermoplastics. A number computational techniques exist for the determination length. In Ahmad et al., [1] method is proposed that treats macromolecular chain as 1D open curve and identifies entanglements by computing linking between two such interacting curves. If curves wind around each other, topological detected. However, measured experiments assumed to be rheological entanglements, which are...
A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> butted-junction split-word line 6T cell in 65nm SOI. design features dual power supplies, unidirectional polysilicon, hierarchical undamped bit lines for enhanced stability performance
A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated. Measured results show an operating range of -40degC to 120degC, speed 6.5 GHz 3.8 for L1-Cache cells L2-Cache cells, respectively, at 1 V 25degC, with high yield. The key features include multi-setting programmable clock block, separate read/write margin circuitry, low noise dynamic decoders, bit select circuitry supported by newly developed fast Monte Carlo technique useful...
We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region this study. In comparison to conventional Si-CMOS technology, proposed improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula>...
High speed level-1 cache applications demand fast single cycle access times and short cycles. Novel circuits that deliver self-resetting CMOS (SRCMOS) techniques are described. Two key elements for are: signal conversion from static to SRCMOS CMOS. These conversions performed by the input receiver output driver circuits. A two-stage address decode scheme minimize gate complexity a high performance "late select 4-to-1" mux in front of drivers also elements. "Sense Hold Amplifier" (SHA) is...
Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. proposed shows strong capability to operate at minimum supply voltage 325 mV, whereas Si-CMOS 6 T unable below 725 which result in an acceptable failure rate.The advance (complementary metal-oxide-semiconductor) based faces inherent limitation aggressive downscaling. Hence, there is a need propose alternatives for cells. Design/methodology/approach This study aims...
The recent report of a high-yielding process with Back-Side Power Delivery (BSPD) using PowerVia, the benefits obtained on an Intel E-core implementation, and imminent deployment PowerVia in High- Volume Manufacturing (HVM), are driving rapid expansion R&D across Si Industry to enable future deployments this seminal innovation. One such example is experimental demonstration back-side contacts (BSCONs), which bring about performance scaling benefits. In paper, we will identify discuss...
In photovoltaic (PV) systems, the irradiation power is main mechanism for energy generation. The PV module's position, orientation, and tilt angle have a considerable impact on both its efficiency durability. roof-installed system thus met domestic industrial requirements. outcome of this research demonstrates that small system, typical panels can provide up to 1KWh more when stacked in landscape orientation than arranged portrait orientation. Connecting solar cells modules essential...
In this letter, we propose a new design of an ultra-low-power and high performance six – transistor (6 T) static random access memory (SRAM) cell using graphene nanoribbon field-effect transistors (GNRFETs). HSPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact GNRFETs model is used to validate the different SRAM cells. The proposed improves in terms power consumption, read data stability, writeability at low supply voltage. also significantly reduces leakage...
Reliability development during the process design of 0.8- mu m and 1.0- nonvolatile memory technology is discussed. The passivation system, polysilicon layer, gate oxide are all analyzed. Passivation reliability in terms data retention, humidity performance, erasability presented for various options. A new failure mechanism associated with electronic emission from poly residue highlighted, optimization to eliminate this shown. effect reoxidized nitrided dielectrics on hot carrier...