A5020189894- Silicon and Solar Cell Technologies
- Semiconductor materials and interfaces
- Semiconductor materials and devices
- Diamond and Carbon-based Materials Research
- Ion-surface interactions and analysis
- Thin-Film Transistor Technologies
- Force Microscopy Techniques and Applications
- Nanowire Synthesis and Applications
- Advancements in Semiconductor Devices and Circuit Design
- 3D IC and TSV technologies
- Copper Interconnects and Reliability
- Advanced Surface Polishing Techniques
- Advanced Materials Characterization Techniques
- Metallurgy and Material Forming
- Integrated Circuits and Semiconductor Failure Analysis
- Electron and X-Ray Spectroscopy Techniques
- Electronic and Structural Properties of Oxides
- Engineering Technology and Methodologies
- Engineering Diagnostics and Reliability
- Advanced Data Storage Technologies
- Carbon Nanotubes in Composites
- Ferroelectric and Negative Capacitance Devices
Intel (United States)
2015-2024
Duke University
1997-2002
A.V. Shubnikov Institute of Crystallography
1993-2002
Russian Academy of Sciences
1993-1996
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
Diamond-coated silicon field emitters were fabricated and investigated. Emission currents of few μA per tip at voltages several hundred volts obtained from very blunt tips with curvature radii up to 3 μm. The values the effective work function calculated Fowler–Nordheim plot in range 0.3 1.2 eV. Two models for an explanation experimental data are proposed.
We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on product in high volume, multiple (M4 M6) incorporate an air gap integration scheme to deliver up 17% RC benefit. Pitch Division patterning is introduced yield capable interconnect with minimum pitch of 52nm.
A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% gain at iso-power over 7. The scaled high-performance offers 50nm gate pitch, 30nm fin pitch minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range 190mV/180mV for N/PMOS, enabling designers to choose between power speed requirements. EUV lithography used extensively simplify process flow improve...
Physical and numerical modeling of impurity gettering from multicrystalline Si for solar cell production has been carried out using Fe as a model impurity. Calculated change nonradiative recombination coefficient minority carriers in the course is used tool evaluating efficiency. A derivation capture cross section precipitates, compared to single atom centers, presented. Low efficiency conventional application process explained by results. The variable temperature modeled predicted provide...
A quantitative model of the electrical activity metallic precipitates in Si is formulated with an emphasis on Schottky junction effects precipitate–Si system. Carrier diffusion and carrier drift space charge region are accounted for. recombination attributed to thermionic emission mechanism transport across rather than surface recombination. It shown that can have a very large minority capture cross-section. Under weak generation conditions, supply carriers found be limiting factor process....
Interconnect process features are described for a 32 nm high performance logic technology. Lower-k, yet highly manufacturable, carbon-doped oxide (CDO) dielectric layers introduced on this technology at three to address the demand ever lower metal line capacitance. The pitches have been aggressively scaled meet expectation density, and resistance electromigration carefully balanced reliability requirements while maintaining lowest possible resistance. A new patterning scheme has used limit...
Single crystalline diamond particles were grown on the ends of sharp silicon tips. The typical form was cubooctahedron with a (111) plane top. Field emission experiments Si emitters single coating demonstrated hysteresis and normal modes. In mode, saturated at about 2 μA. Fowler–Nordheim plots for data points below saturation limit nonlinear. Transformation from to behavior occurred increasing voltage. A modified model through dielectric layers proposed explanation properties diamond.
We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack introduce the SOC family of interconnects. Enhancement includes improved RC intrinsic capacitance for metal layers over a range process versions stacks offered optimal cost density targeted various applications.
In silicon solar cell fabrication, impurity gettering from Si by an aluminum layer and indiffusion of Al for creating the back surface field (BSF) are inherently carried out in same process. We have modeled these two processes analyzed their impact on efficiency. The output modeling is used as input calculation efficiency gain obtained a function duration. To check relative contributions BSF improving efficiency, effects evaluated together well separately. It found that, cells fabricated low...
We have calculated the nucleation energy barrier of voids and vacancy (V) type dislocation loops in Si under V-supersaturation conditions. The V-type is higher than that by more one order magnitude, with former exceeding 35 eV at attainable levels. Thus, can be nucleated, but not loops. This provides an explanation for observations that, crystals grown conditions, exist do not. Voids seriously degrade device gate oxide integrity. It highly probable D-type swirl defects are nanoscopic voids....
During Si crystal growth, nucleation and growth of voids vacancy-type dislocation loops under vacancy supersaturation conditions have been modeled. From barrier calculations, it is shown that can be nucleated, but not loops. The homogeneous rate has calculated for different temperatures by assuming enthalpy formation. void process using a moving boundary formulation. Matching the results simulations taking into account competition between two processes, limited time available, cooling rate,...
A brief review of performance-limiting processes in a commercial solar cell fabricated on low-cost substrate is given. Higher efficiencies require effective gettering precipitated impurities present at the defect clusters, and improved process designs. Overcoming these limitations expected to lead 18%–20% efficiencies.