A5035806887- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Silicon Carbide Semiconductor Technologies
- Electromagnetic Compatibility and Noise Suppression
- Eosinophilic Disorders and Syndromes
- Nanowire Synthesis and Applications
- Cardiac Structural Anomalies and Repair
- Interconnection Networks and Systems
- Pericarditis and Cardiac Tamponade
- Chronic Myeloid Leukemia Treatments
- Healthcare cost, quality, practices
- Chronic Lymphocytic Leukemia Research
- Innovations in Medical Education
- Electrical Contact Performance and Analysis
- Cardiac tumors and thrombi
- Clinical practice guidelines implementation
- Power Line Communications and Noise
- Thin-Film Transistor Technologies
- Cloud Computing and Resource Management
Mayo Clinic in Florida
2022-2024
WinnMed
2024
Jacksonville College
2022-2023
Intel (United States)
2005-2015
Hewlett-Packard (United States)
2005
Motorola (United States)
2004
A 14nm logic technology using 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical layers, and air-gapped interconnects at performance-critical layers is described. The feature rectangular fins 8nm fin width 42nm height, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> generation high-k metal gate, 6 strained...
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three interconnect layers is described. For high density, a novel self-aligned contact over active gate process elimination of the dummy cell boundaries are introduced. The feature rectangular fins 7nm fin width 46nm height, 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance is presented. Transistor length scaled down to while not scaling the oxide as a means improve reduce power. Increased NMOS PMOS drive currents are achieved by strain junction engineering. 193nm lithography along APSM mask used on critical provide aggressive design rules 6-T SRAM cell size 0.57/spl mu/m/sup 2/....
A 32 nm generation logic technology is described incorporating 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -generation high-k + metal-gate technology, 193 immersion lithography for critical patterning layers, and enhanced channel strain techniques. The transistors feature 9 Aring EOT gate dielectric, dual band-edge workfunction metal gates, 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> strained silicon, resulting in the...
A 32 nm logic technology for high performance microprocessors is described. 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation high-k + metal gate transistors provide record drive currents at the tightest pitch reported any or 28 technology. NMOS are 1.62 mA/um Idsat and 0.231 Idlin 1.0 V 100 nA/um I <sub xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> . PMOS 1.37 0.240 The impact of SRAM cell array size on Vccmin reported.
This paper details the transistor aging and gate oxide reliability of Intel's 14nm process technology. technology introduces 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> generation tri-gate 4 xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> high-κ dielectrics metal-gate electrodes. The metrics reported here highlight gains attained through optimizations as well intrinsic challenges from device scaling.
This paper compares the performance and inter-die variability of doped undoped channel multiple-gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent narrow-width As such, transitions for devices will likely incur minimal impact. To match low wide-width devices, conversions is necessary. Furthermore, good short-channel control has be maintained since exhibit increase sensitivity Tbody relative due enhanced fully-depleted electrostatics
Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict Gate oxide lifetime (TDDB) at use. This paper highlights low (low-V) data for accurate assessment HK+MG provides further evidences from both transistor-...
Device architectures incorporating multiple gate structures have been proposed to allow transistor scaling beyond the planar MCSFET integrations. These device can improve performance such as better short channel and reduced leakage. In addition additional surface electrodes offers new circuit possibilities dynamic threshold voltage control an RF mixer are demonstrated. It is desirable fabricate multi-gated devices with single on sides this has demonstrated successfully.
Abstract not Available.
Clinical guidelines have become an integral part of clinical care. We assessed professional society-based from 2012 to 2022 elucidate the trends in numbers documents, recommendations, and classes recommendations. Our results found that 40% do not follow all recommendations made by Institute Medicine for trustworthy documents. There has been a significant increase documents cardiology, gastroenterology, hematology/oncology. In addition, more than 20,000 there was variability different...
Measurement-based multi-port (/spl ges/8) s-parameter models are developed for HSS links. These provide wide-bandwidth and large number of ports worst-case differential coupling simulations even when the test vehicles have only limited accessibility.