A5006123246- Integrated Circuits and Semiconductor Failure Analysis
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Methane Hydrates and Related Phenomena
- Boron and Carbon Nanomaterials Research
- Additive Manufacturing and 3D Printing Technologies
- Hydrocarbon exploration and reservoir analysis
- Photonic and Optical Devices
- Force Microscopy Techniques and Applications
- Semiconductor Lasers and Optical Devices
- 3D IC and TSV technologies
- CO2 Sequestration and Geologic Interactions
- Advanced ceramic materials synthesis
- Aluminum Alloys Composites Properties
- Laser-induced spectroscopy and plasma
- Ferroelectric and Negative Capacitance Devices
- Geological and Geophysical Studies
- Electronic Packaging and Soldering Technologies
- Geophysical and Geoelectrical Methods
- Near-Field Optical Microscopy
- Semiconductor materials and interfaces
- Geology and Paleoclimatology Research
- Electrostatic Discharge in Electronics
- Laser Material Processing Techniques
- VLSI and Analog Circuit Testing
Taiwan Semiconductor Manufacturing Company (Taiwan)
2015-2024
Lawrence Livermore National Laboratory
2018-2021
Lawrence Berkeley National Laboratory
2020
Southern Taiwan Science Park
2019
Taiwan Semiconductor Manufacturing Company (United States)
2015
Intel (United States)
2006-2012
University of California, San Diego
2001-2002
Nortel (Canada)
2001
Simon Fraser University
2001
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile HPC applications. This industry-leading features, the first time, full-fledged EUV, high mobility channel (HMC) finFETs with densest 0.021µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> HD SRAM. true is a full node scaling from our successful 7nm [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The successfully passed...
High-K (HK) and Metal-Gate (MG) transistor reliability is very challenging both from the standpoint of introduction new materials requirement higher field operation for performance. In this paper, key unique HK+MG intrinsic mechanisms observed on 32nm logic technology generation presented. We'll present similar to or better than 45nm generation.
Fabrication of boron carbide (B4C) parts through direct ink writing at room temperature has been demonstrated. The 3D printed B4C were made from aqueous, thixotropic consisting particles with a solid loading ranging 50.0 to 59.3 vol%. porous infiltrated molten aluminum (Al) form dense B4C-Al cermet. Simple cubic samples varied spacing between filaments tailor the density profile within part. Rockwell hardness such ranges 20 90 Ra (60 kg) depending on overall structure. Parts variable...
Gate oxide breakdown is a key mechanism limiting IC lifetime. Breakdown typically characterized on test capacitors, but estimating product reliability from such results requires making number of often-untested assumptions. This work compares the predictions capacitor-based models to accelerated lifetest logic CPU products. For technology studied, failure rate was somewhat lower than model prediction, and analysis indicated that an important factor different sensitivities circuits vs. cache...
To keep up with the dominance in field of leading semiconductor technology innovation, TSMC has announced risk production its most advanced 5nm CMOS logic node [1] using full-fledged EUV and high mobility channel (HMC) FinFETs. Supporting state art mobile SOC chips HPC application needs, this provides ~1.8x improvement density, 15% speed gain 30% power reduction as compared to previous 7nm generation - [2] . This paper, for first time, brings out detailed reliability attributes from device...
Abstract Gas hydrates possess lower electrical conductivity (inverse of resistivity) than either seawater or ice, but higher clastic silts and sands, such that electromagnetic methods can be employed to help identify their natural formation in marine permafrost environments. Controlled laboratory studies offer a means isolate quantify the effects changing individual components within gas‐hydrate‐bearing systems, turn yielding insight into behavior systems. Here we investigate properties...
Two-dimensional (2D) carrier concentration profiling using scanning spreading resistance microscopy (SSRM) has been carried out on molecular beam epitaxy-grown GaAs and InP dopant calibration samples. The current transport mechanisms between the diamond-coated SSRM tip III–V semiconductor cleaved surface (110) was investigated as a function of via current–voltage (I–V) measurement. A positive or negative bias applied while over each region (1016–1019 cm−3). results were compared to simulated...
Abstract CO 2 and CH 4 clathrate hydrates are of keen interest for energy carbon cycle considerations. While both typically form on Earth as cubic structure I (sI), we find that pure hydrate exhibits over an order magnitude higher electrical conductivity ( σ ) than at geologically relevant temperatures. The was obtained from frequency‐dependent impedance Z measurements made polycrystalline (CO ·6.0 ± 0.2H O by methods here) with 25% gas‐filled porosity, compared (CH ·5.9H O) formed measured...
Two-dimensional carrier profiling using scanning spreading resistance microscopy (SSRM) has recently been reported for Si- and InP-based structures. In this article, we report SSRM measurements solely on III–V material-based We have studied GaAs InP doping staircase structures, prepared molecular-beam epitaxy. These structures were then used as calibration standards the of density in state-of-the-art III–V-based optoelectronic devices. discovered that data can be obtained with either...
Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict Gate oxide lifetime (TDDB) at use. This paper highlights low (low-V) data for accurate assessment HK+MG provides further evidences from both transistor-...
The transformation of boron nitride from the cubic to hexagonal phase has been investigated between 1560 and 1660 °C. High-purity cBN powders three different particle sizes (<0.5 μm, 2–4 μm 35–45 μm) were heat treated at ambient pressure in a dry flowing helium atmosphere over this temperature range for up 8 h. Microscopy reveals surface growth hBN on particles, although morphology texture is largest particles (35–45 smaller μm). X-ray diffraction was used measure weight fraction each powder...
Scanning spreading resistance microscopy (SSRM) is a promising new tool for dopant profiling in semiconductor materials. We present the results of SSRM study cross section metalorganic chemical vapor deposited grown optoelectronic structure. The measurements are compared with secondary ion mass spectrometry (SIMS) and excellent spatial agreement obtained. However, we find that obtaining quantitative SIMS complicated by differing nonlinear I-V characteristics n- p-type InP. suggest would...
In this study, a reliability study from device, circuit aging, and product characterization is systematically presented for the state-of-the-art 7nm FinFETs. The Bias-Temperature Instability (BTI) Hot Carrier Injection (HCI) FinFET are compared with past 10nm devices, as well novel aging framework to estimate BTI recovery self-heat effect in early design. Moreover, correlation between SRAM static noise margin (SNM) induced Vt drift consolidates domination of initial spread SNM shift. A new...
This work presents a systematic study of the off-state drain bias time dependent dielectric breakdown (TDDB) mechanism, especially for short channel transistors in advanced FinFET technologies. The sub-threshold leakage current was found to play key role determining TDDB degradation. Short show higher electric field (E-Field) near side due increase and hence, lifetime is seen scale with decrease length. Moreover, additional process optimizations, such as source/drain proximity push,...
In this paper, the detailed TDDB models of HK/IL gate stack for N/PMOS were established through analysis oxide trap generation in FinFET technology. We systematically characterized traps HK and IL layers by AC admittance SILC spectrum methodologies. found that deep layer plays decisive role NMOS TDDB, while formation are critical to PMOS TDDB. addition, be highly responsible permanent damage during stress, such that, physical mechanisms breakdown devices can successfully explained...
Advanced packaging platforms such as 3DIC and 3D Fabric have encountered increased reliability risks with advanced architectures CoWoS (Chip on Wafer Substrate), InFO (Integrated Fan Out), SoIC (System Integrated Chips). Material analysis, mechanical, board/system level tests were conducted to reduce concerns improve the robustness of architecture. To further evaluate lifetime these new extended test duration is implemented. Using previously mentioned novel testing approaches, technology...
In this paper, the physical explanation of time dependent dielectric breakdown (TDDB) power law lifetime model is successfully interpreted through analysis oxide trap generation in HK/IL gate stack NMOS-FinFET technology. The experiments are performed using stress induced leakage current (SILC) spectrum methodology. It found that TDDB has a strong correlation to deep generation. Shallow traps, on other hand, play role increase SILC behavior and also promote further formation during...
As more research findings have shown the correlation between ordering in organic semiconductor thin films and device performance, it is becoming essential to exercise control of through structural tuning. Many recent studies focused on influence side chain engineering polymer packing orientation films. However, impact size conformation aromatic surfaces film has not been investigated great detail. Here we introduce a disk-shaped polycyclic hydrocarbon building block with large π surface,...
Abstract Methane hydrate was synthesized from pure water ice and flash frozen seawater, with varying amounts of sand or silt added. Electrical conductivity determined by impedance spectroscopy, using equivalent circuit modeling to separate the effects electrodes gain insight into conduction mechanisms. Silt increase hydrate; we infer contaminant NaCl contributing in hydrate, values agreement resistivities observed well logs through hydrate‐saturated sediment. The addition lowers seawater an...
Boron carbide (B4C) is one of the hardest materials in existence. However, this attractive property also limits its machineability into complex shapes for high wear, hardness, and lightweight material applications such as armors. To overcome challenge, negative additive manufacturing (AM) employed to produce geometries boron carbides at various length scales. Negative AM first involves gelcasting a suspension 3D-printed plastic mold. The mold then dissolved away, leaving behind green body...
A new TDDB lifetime model is proposed to predict for AC inverter-like stress in FinFET device. The governing by four mechanisms, including voltage switching, electron detrapping, HCI and hole injection. Among them, switching detrapping improve lifetime; while injection degrade the lifetime.
In this paper, several protection schemes for the plasma-induced damage (PID) from well-side antennas are proposed. The PID components made of diodes or ESD-like clamps used to either balance potentials between wells clamp gate-to-source voltages victim gates. These and way insert have been verified by a variety test structures designed in 0.13µm BCD (Bipolar-CMOS-DMOS) process where NBL (N-type Buried Layer) is as isolation well.
In this paper, we propose layout guidelines to significantly mitigate the charging damage from well-side antennas in separated power domains. We specifically focus on circuit topologies that consist of aggressor-victim pairs. The are based silicon data test patterns cover adequate combinations different geometries isolation wells, metals, and vias, as well configurations. method has been verified 0.13µm BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer) well.
The increasing impact of self-heating effect (SHE) in complex FinFET structure is a serious reliability concern. Although the evaluation SHE has become extremely arduous; this work proposes an in-situ layout based experimental solution to find out precise thermal time constant (T <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> ) due on advanced devices, even with application very pragmatic 'circuit-like' gate and drain input waveforms....