A5060239328- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- 3D IC and TSV technologies
- VLSI and Analog Circuit Testing
- VLSI and FPGA Design Techniques
- Ferroelectric and Negative Capacitance Devices
- Copper Interconnects and Reliability
- Radio Frequency Integrated Circuit Design
- Silicon Carbide Semiconductor Technologies
- Analog and Mixed-Signal Circuit Design
- Embedded Systems Design Techniques
- Advancements in Photolithography Techniques
- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Electrostatic Discharge in Electronics
- Electronic Packaging and Soldering Technologies
- Advancements in PLL and VCO Technologies
- Distributed and Parallel Computing Systems
- Robotic Mechanisms and Dynamics
- Green IT and Sustainability
- Advanced Battery Technologies Research
- Thin-Film Transistor Technologies
- IoT and Edge/Fog Computing
Taiwan Semiconductor Manufacturing Company (Taiwan)
2019-2025
Qualcomm (United States)
2007-2016
Market Matters
2009-2016
Qualcomm (United Kingdom)
2007-2015
Motorola (United States)
2002-2003
Advanced Micro Devices (United States)
1998-2003
Advanced Micro Devices (Canada)
2002
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile HPC applications. This industry-leading features, the first time, full-fledged EUV, high mobility channel (HMC) finFETs with densest 0.021µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> HD SRAM. true is a full node scaling from our successful 7nm [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The successfully passed...
The explosive growth of smart mobile wireless devices in recent years has fundamentally transformed the semiconductor industry. Mobile system-on-chips (SoCs) become leading product driver for technology definition and manufacturing This trend was first observed 28 nm will continue 20 nm, 16/14 10 adoption production ramp. Recent SoC performance increase achieved mainly through silicon scaling, from single to dual- quad-core. For SoCs offering new exciting user-experiences, longer battery...
Fringing-induced barrier lowering (FIBL), a new anomalous degradation in device turn-off/on characteristics sub-100 nm devices with high-K gate dielectrics, is reported. FIBL clearly evident for K > 25 and worsens as increases (without buffer oxide). With oxide, can be completely suppressed < 25, partially higher K. the length becomes shorter. Complete removal of dielectrics on active area induces smaller FIBL.
Despite recent advances, low-voltage operation remains one of the key approaches for power reduction. However, continuous scaling SRAM bit cell, in advanced technologies, based on transistor's minimum geometry is accompanied by increased random threshold voltage variations that limit SRAM's operating (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</sub> ). The introduction FinFET transistors has provided better short channel effects and...
Although near-threshold (Vth) operation is an attractive method for energy and performance-constrained applications, it suffers from problems in terms of circuit stability, particularly, static random access memory (SRAM) cells. This brief proposes a near-Vth 9T SRAM cell implemented 22-nm FinFET technology. The read buffer the proposed ensures stability by decoupling stored node bit-line improves performance using one-transistor path. Energy standby power are reduced eliminating sub-Vth...
Although near-threshold voltage (NTV) operation is an attractive means of achieving high energy efficiency, it can degrade the circuit stability static random access memory (SRAM) cells. This paper proposes NTV 7T SRAM cell in a 14 nm FinFET technology to eliminate read disturbance by disconnecting path from bit-line cross-coupled inverter pair using transmission gate. In proposed cell, half-select issue resolved, meaning that no write-back required. A folded-column structure applied reduce...
In this paper, the design space, including fin thickness <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(T_{\rm fin})$ </tex></formula> , height Notation="TeX">$(H_{\rm fin})$</tex></formula> ratio of bit-cell transistors, and surface orientation, is researched to optimize stability, leakage current, array dynamic energy, read/write delay FinFET SRAM under layout area constraints. The simulation...
A 135-Mb 0.021-μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) charge-sharing lower cell-VDD (CS-LCV) techniques to reduce minimal supply voltage. Flying (FBL) architecture is also improve...
To keep up with the dominance in field of leading semiconductor technology innovation, TSMC has announced risk production its most advanced 5nm CMOS logic node [1] using full-fledged EUV and high mobility channel (HMC) FinFETs. Supporting state art mobile SOC chips HPC application needs, this provides ~1.8x improvement density, 15% speed gain 30% power reduction as compared to previous 7nm generation - [2] . This paper, for first time, brings out detailed reliability attributes from device...
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL BEOL holistically. Speed-power performance plainly scaled N7 turns out be degraded compared previous node. wire resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">wire</sub> ) multiplied logic gate input pin cap (C xmlns:xlink="http://www.w3.org/1999/xlink">pin</sub> ), ×C , is identified as a major limiter power at N7. Reducing...
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL BEOL holistically. Speed-power performance plainly scaled N7 turns out be degraded compared previous node. wire resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">wire</sub> ) multiplied logic gate input pin cap (C xmlns:xlink="http://www.w3.org/1999/xlink">pin</sub> ), ×C , is identified as a major limiter power at N7. Reducing...
As device dimension shrinks less than 65nm, the propagation delay, crosstalk noises, and power dissipation due to RC (Resistance Capacitance) coupling becomes significant. Cu LK (Low-k dielectric) material have been introduced reduce such delays allow higher speed better performance. However, since dielectric with low-k value usually possesses large amount of porosity, its mechanical properties are degraded significantly which leads fragile silicon backend structure. This in turn brings...
By optimizing the design of inductor a voltage-controlled oscillator for performance without area constraint and fully filling underneath with other necessary components, performance, including efficiency, can be simultaneously optimized. In addition to varactors cross-coupled transistor pairs, current source, VCO buffers, frequency dividers, MOS bypass capacitors placed an VCO. Exploiting this, 4.3-5.6-GHz 14 400 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, cost effective 28 nm 4G SOC has been crafted. This design strategy uses two sets rules and 7 different Vt cells with optimal power gating achieve 2.4× increase in gate density, 55% decrease 30% gain frequency respect 45 counterpart. Relevant technical tradeoffs between design/technology interactions are...
In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to bit-cell structures SRAM schemes that were previously proposed using symmetric IG-MOSFET is analyzed. addition, a novel scheme with improve read stability and writeability by controlling back gates pass-gate pull-up transistors. New array architecture also suggested prevent degradation in half-selected cell, where word line selected but bit unselected. The previous SRAMs (IG-SRAMs) fail simultaneously...
We report for the first time a highly selective CVD Co deposition on Cu to fill 45nm diameter 3:1 aspect ratio via in dual damascene structure. have achieved void-free of via, demonstrating that bottom-up with is potentially viable approach. Defect formation and control process device integration are discussed. This provides an opportunity reduce resistance shrink minimum metal 1 (M1) area aggressive standard cell size scaling as needed 7nm technology.
The degradation of the read stability and write ability static random-access memory (SRAM) is becoming a critical problem in deep submicrometer technology. To solve this problem, there are many SRAM cell design options such as preferred cells assist circuits. In addition, extremely thin silicon-on-insulator (ETSOI) with buried oxide offers an independent back-gate control. paper, previously proposed back-gate-assist circuit schemes analyzed. From this, we propose read-preferred write-assist...
A high speed IRIW two port 32Kbit (128×256) SRAM with single 6T bitcell macro is proposed. Read-Then-Write (RTW) double pump CLK generation circuit TRKBL bypassing proposed to enhance read performance. Double metal scheme applied improve signal integrity and overall operating cycle time. Local Interlock Circuit (LIC) introduced in Sense-Amp reduce active power push Fmax further. The silicon results show that the slow corner wafer was able achieve 4. 24GHz at 1.0V/100°C 5nm FinFET technology.
Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin required meet the target yield because SRAM according Vcc shows "dual slope". In this paper, root causes of slope" are analyzed. Both side effect bitcell on also considered accurately project Vccmin, which results in 40 mV increase 99% for 32 nm HK/MG planar 1 M SRAM. The compared 32nm and FinFET SRAMs with (HD) doping (LD). Under effect, channel length adjustment pass gate transistor...
Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional variations not previously seen in process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of introduced from GDIM and GGIM, their sensitivity to circuit layout. Design optimization verification mechanisms are developed mitigate process induced analog circuits. After...
A near-threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) operation circuit is important for both energy- and performance-constrained applications. The conventional 6-T SRAM bit-cell designed super-V cannot achieve the target margins such as hold stability, read write ability in near-V region. recently proposed bit-cells with buffer suffer from problems of low 0 sensing margin large 1 time This paper proposes a...