A5054699684- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- VLSI and Analog Circuit Testing
- VLSI and FPGA Design Techniques
- Advancements in PLL and VCO Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Photonic and Optical Devices
- Interconnection Networks and Systems
- Advanced Memory and Neural Computing
- Radio Frequency Integrated Circuit Design
- Radiation Effects in Electronics
- CCD and CMOS Imaging Sensors
- COVID-19 Clinical Research Studies
- Embedded Systems Design Techniques
- Organic Electronics and Photovoltaics
- Metal and Thin Film Mechanics
- SARS-CoV-2 and COVID-19 Research
- Ferroelectric and Negative Capacitance Devices
- Innovative Energy Harvesting Technologies
- 3D IC and TSV technologies
- Quantum Computing Algorithms and Architecture
- Semiconductor Lasers and Optical Devices
- Advanced Fiber Optic Sensors
Taiwan Semiconductor Manufacturing Company (Taiwan)
2023-2025
National Yang Ming Chiao Tung University
2002-2024
Chi Mei Medical Center
2022-2024
National Taipei University of Technology
2015
Taiwan Semiconductor Manufacturing Company (United States)
2014
Advanced Semiconductor Engineering (Taiwan)
2013
Taichung Veterans General Hospital
2013
National Taiwan University of Science and Technology
2006
University of Illinois Urbana-Champaign
1989-2003
Urbana University
1991
In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of static random-access memory (SRAM) cross-coupled inverter pair. read mode, an access buffer designed isolate storage node from path for better robustness and leakage reduction. The bit-interleaving scheme allowed incorporating SRAM with additional wordlines (WWL/WWLb) soft-error tolerance. A 1-kb 4-to-1 bit-interleaved implemented in 65-nm bulk CMOS technology. experimental results...
Pentacene organic thin-film transistors (OTFTs) with a high-kappa HfLaO dielectric were integrated onto flexible polyimide substrates. The pentacene OTFTs exhibited good performance, such as low subthreshold swing of 0.13 V/decade and threshold voltage -1.25 V. field-effect mobility was cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots at an operating only 2.5 These characteristics are attractive for high-switching-speed...
We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. measured good device performance, such as low subthreshold swing of 0.078 V/dec, threshold voltage -1.3 V, and field-effect mobility 0.71cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / Vldrs . This occurred along with an ON-OFF state drive current ratio 1.0 times 10 xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> , when the...
A process, voltage, and temperature (PVT) sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high accuracy, low power, wide voltage range portable applications. Conventional sensors rely on ADC digital output code conversion. The generates clock frequency proportional to the measured temperature, converts into corresponding code. generated still under influence of PVT variations. Two distinct process monitoring are also enhance...
The problem of diagnosis and spare allocation for random-access memory (RAM) with coupling faults is addressed. A number algorithms RAM row column redundancy have recently been proposed. These procedures, however, restricted to repair stuck-at faults. authors examine both in RAMs utilizing rows columns. It shown that a fault repaired if its cell replaced by or coupled column. By specifying the cell, amount required given set may be reduced. procedure provided locate as well graph model used...
Diagnosis strategies are investigated for repairable VLSI and WSI structures based on integrated diagnosis repair. Knowledge of the repair strategy, probability each unit being good, expected test time is used by algorithm to select units testing. The general problem described, followed an examination a specific case. For k-out-of-n structures, complete proof given optimal procedure Y. Ben-Dov (1981). A compact representation which requires O(n/sup 2/) space can be generated in time....
Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low consideration, primary concerns of are stability and reliability instead performance. In this paper, proposed 9T bit-cell enhances write ability by cutting off positive feedback loop inverter pair. read mode, isolated path storage node enlarge SNM. Besides, subthreshold enable implementation bit-interleaving structure which achieves soft-error tolerance. The able...
By using HfAlO as a capping layer on SiON, MoN/HfAlO/SiON p-MOSFETs show an effective work function of 5.1 eV, low threshold voltage -0.1 V, and peak hole mobility 80 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /(Vmiddots) at small equivalent oxide thickness 0.85 nm. These self-aligned gate-first processes, with standard ion implantation 1000degC rapid thermal annealing, are fully compatible current very large scale integration...
In this paper, a new single-ended 6-T SRAM cell is proposed. It has very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability achieved by these two approaches. A current-mode sensing amplifier also presented. This sense small swing bitline, equipping with high noise-rejection PVT-tolerance ability. low-swing 3-port 64times32-bit macro simulated in TSMC...
Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low consideration, primary concerns of are stability and reliability instead performance. In this paper, proposed 9T bit-cell enhances write ability by cutting off positive feedback loop inverter pair. read mode, isolated path storage node enlarge SNM. Besides, subthreshold enable implementation bit-interleaving structure which achieves soft-error tolerance. The able...
Given the limited space and cooling capacity in dilution refrigerators, it is challenging to scale number of qubits for a fault-tolerant quantum computer (QC). In this paper, we study custom-scaled CMOS technology overcome constraints refrigerators. With Cryo-Design/ Technology CoOptimization (Cryo-DTCO) an advanced node, one can then reduce control power from 26.8 mW/ qubit 8.4 $(\sim 0.31 \times)$. Projections suggest may be sufficient enable error corrections via surface codes computing.
This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port (P2P-SRAM) and single-port (SP-SRAM) functions in one compiler. Unlike conventional that always performs read first, this work enables dynamic read-or-write-first selection write-through function. It can improve SP-SRAM function speed by 90% faster than of the read-first design. An area-free constant-negative-level write driver (CNL-WD), which is suitable compiler development, used to Vmin...
A process, voltage and temperature (PVT) sensors with dynamic selection are proposed for environmental management in the ultra-low frequency scaling (DVFS) system. The process (PV) initially monitor variation. With known information, PV can real-time provide variation status. sensor has six sensitive ring oscillators (TSROs) generating proportional to temperature. It dynamically selects proper TSRO convert into digital readings according status provided by sensors. information from sensors,...
Crosstalk between bitlines induces read failure and limits the coverage of applicable code-patterns for high-speed contact/via-programming read-only memories (ROMs) in SoC. Owing to variation bitline loading across code-patterns, amount coupled noise on an accessed is code-pattern-dependent. This crosstalk effect worsens, with larger coupling capacitance smaller intrinsic loading, as technology node shrinks. study proposes dynamic virtual guardian (DVG) techniques ROM macros compilers...
A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed TSMC 130nm CMOS technology model. modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive PVT variations good for digitally-controlled element. lock-in time could be reduced down 14 reference clock cycles, enhance the operation range based on LADE/binary co-operate effort. timing error caused by...
A high efficiency power management system for solar energy harvesting applications is proposed. The receives from photovoltaic (PV) cell and generate different voltage levels, they are 1V~0.3V analog circuitry low digital circuitry, -1.2V super-cutoff technique in memory 10V FLASH or I/O components. great varieties suitable green integrated regulator SoC electronics. also contains a rechargeable battery which charged by multi-phase maximum tracking (MPT) with the PV module. With MPT of can...
A multiple supply voltage scheme is an emerging approach to reduce power dissipation. The requires a level converter as bridge for different domains. Conventional converters fail work in sub-threshold region due the pull-down devices and pull-up operate super-threshold respectively. By employing diode-connected PMOS transistors, multiple-threshold-voltage CMOS (MTCMOS), stack leakage reduction techniques, proposed cross-coupled achieves small propagation delay, low consumption, best...
With the emergence of Omicron variant severe acute respiratory syndrome coronavirus 2, Taiwan has encountered greatest disease 2019 (COVID-19) pandemic since 2022 spring. We analyzed characteristics, vaccinations, and outcomes hospitalized COVID-19 patients quarantined in a dedicated ward. This retrospective study enrolled wards district hospital southern from May to July 2022. assessed in-hospital mortality, length stay (LOS), ward LOS. Among 209 patients, mortality rates were 20.7% 29.7% (...
The voltage-/temperature-induced delay estimation error of conventional logical effort is much more severe in near/sub-threshold region. In this paper, super-/near-/sub-threshold models are proposed to eliminate caused by voltage and temperature variations. These establish over the four different nanoscale CMOS generations. They also take environmental parameter variations with wide supply 0.1~1V full -50~125°C range into account. simulation results using UMC 90-nm, PTM 65-, 45- 32-nm bulk...
An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) phase detector (PFD). A modified digitally delay element (DCDE) characteristics its monotonicity insensitivity to PVT variations is presented for the DCO design. new PFD architecture that can finish comparison adjustment in one reference cycle presented. This operate from 300MHz 1GHz, achieve acquisition fifteen clock cycles (worst...
In this paper, an ultra-low power (ULP) 16Kb SRAM-based first-in first-out (FIFO) memory is proposed for wireless body area networks (WBANs). The FIFO capable of operating in voltage (ULV) regime with high variation immunity. An ULP near-/sub-threshold 10 transistors (10T) SRAM bit-cell to be the storage element improving write ULV and eliminate data-dependent bit-line leakage. also features adaptive control circuit, counter-based pointers, a smart replica read/write unit. implemented...