A5071608520- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Electromagnetic Compatibility and Noise Suppression
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Electrostatic Discharge in Electronics
- Ultra-Wideband Communications Technology
- Copper Interconnects and Reliability
- 3D IC and TSV technologies
- VLSI and FPGA Design Techniques
- VLSI and Analog Circuit Testing
- Gyrotron and Vacuum Electronics Research
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Antenna Design and Analysis
- Interconnection Networks and Systems
- Wireless Body Area Networks
- Digital Filter Design and Implementation
- Magnetic Field Sensors Techniques
- Electrical and Bioimpedance Tomography
Qualcomm (United States)
2015-2024
Qualcomm (United Kingdom)
2015-2021
IMEC
2001-2016
KU Leuven
2001-2012
ON Semiconductor (Belgium)
2007
Imec the Netherlands
2004
The successful realization of a wireless body area network (WBAN) requires innovative solutions to meet the energy consumption budget autonomous sensor nodes. radio interface is major challenge, since its power must be reduced below 100 /spl mu/W (energy scavenging limit). emerging ultra-wide-band (UWB) technology shows strong advantages in reaching this target. First, most complexity an UWB system receiver, which perfect scenario WBAN context. Second, very little hardware transmitter offers...
We investigate the impact of wire geometry on resistance, capacitance, and RC delay Cu/low-k damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu wires, integrated with Ru-based liner, currently investigated 7 nm logic technology node. capacitance simulated means 2D field solver (Raphael) Synopsys. line dimensions analyzed case 32 pitch interconnects, which are representative show that aspect ratios...
More and more system-on-chip designs require the integration of analog circuits on large digital chips will therefore suffer from substrate noise coupling. To investigate impact circuits, information is needed about generation. In this paper, a recently proposed simulation methodology to estimate time-domain waveform applied an 86-Kgate CMOS ASIC low-ohmic epi-type substrate. These results have been compared with measurements difference between simulated measured rms voltage less than 10%....
By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling provides 34% energy gain from 6T cells. The loss in speed of 15% recovered different front-end solutions. Air gap spacers are the most efficient booster provide an extra energy. Lateral Nanowires compete FinFETs 12% if tight vertical 10 nm between wires achieved.
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% 45%. show that the performance these devices is substantially improved by high-pressure (HP) deuterium (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) anneal, which ascribed to 2x reduction interface trap density xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ). Furthermore, it found...
We investigate the dependence of Cu via resistance on dimensions, shape, misalignment, and Co prefill level by means a novel resistivity model, calibrated to actual wires silicon integrated into Synopsys Raphael tool. For this paper, we consider case 16 12nm self-aligned vias, which are representative for 7 5nm logic technology nodes, respectively. Process emulations performed using Sentaurus Explorer tool in order generate 3-D models investigated structures. Finally, is extracted through...
A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. topology selection study demonstrates that the quadrature analog correlation a good architecture choice when energy consumption must be minimized. The operates in 3.1-5 GHz band of UWB FCC spectrum mask on channels 500 MHz bandwidth. pulse operation done domain order to reduce ADC sampling speed down repetition rate, thereby reducing power consumption. comprises low-noise amplifier with full...
This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design have been implemented and measured on a mixed-signal chip, fabricated in 0.35 /spl mu/m process an EPI-type with 10 Omega/cm EPI resistivity 4 layer thickness. The test chip contains one reference two low-noise designs the same basic architecture. Measurements show more than factor of 2 average r.m.s. penalties 3% area 4% power employing supply-current waveform-shaping technique...
Substrate noise caused by large digital circuits will degrade the performance of analog located on same substrate. To simulate this degradation, total amount generated substrate must be known. Simulating is however not feasible with existing circuit simulators and detailed models due to long simulation times high memory requirements. We have developed a methodology generation at higher level. Not only does take coupling from switching gates into account, but also power supply included. This...
A 3-to-5GHz quadrature analog correlation RX for UWB impulse radio draws 16mA at 20Mpulses/s, making it suitable low-power low-data-rate applications. The is fully integrated in a CMOS 0.18μm process and comprises an LNA, LO generation mixers, baseband filtering, integrator, timing circuitry, ADC
Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with clock frequency, substrate does not have this scaling due to resonances in transfer function of supply current substrate. This paper addresses practical technique estimate frequency spectrum large mixed-mode System-on-Chip (SoC) multiple supplies and embedded memories. The results been verified measurements on 60-MHz 220-Kgates telecom SoC implemented 0.35 μm CMOS process an...
Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate their dependencies on parameters need be well understood. In paper, we show downscaling technology, due supply coupling becomes dominant mechanism when chip directly biased digital ground. With Kelvin ground biasing other hand, source/drain capacitive mechanism. Further,...
Rather than continue the expensive and time-consuming quest for transistor replacement, authors argue that 3D chips coupled with new computer architectures can keep Moore's law on its traditional scaling path.
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL BEOL holistically. Speed-power performance plainly scaled N7 turns out be degraded compared previous node. wire resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">wire</sub> ) multiplied logic gate input pin cap (C xmlns:xlink="http://www.w3.org/1999/xlink">pin</sub> ), ×C , is identified as a major limiter power at N7. Reducing...
System scaling enabled by Moore's is increasingly challenged the scarcity of resources such as power and interconnect bandwidth. This has become more challenging under requirements seamless interaction between big data instant (Figure MM-1). Instant generation requires ultra-low-power devices with an "always-on" feature at same time high-performance that can generate instantly. Big abundant computing, communication bandwidth, memory to service information clients need.
In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of supply current. We demonstrate an effective combination two methodologies for ground-bounce reduction based shaping current: 1) introducing intentional skews network and 2) frequency modulation system clock. The former technique reduces time-domain as well spectral power current by spreading simultaneous switching activities....
Substrate noise is a major obstacle for mixed-signal integration. Ground bounce contributor to substrate generation due the resonance caused by inductance and Vdd-Vss admittance that consists of on-chip digital circuit capacitance MOS transistors, decoupling, parasitics arising from interconnect. In this paper, we address: 1) dependence on different states circuit, supply voltage, interconnect, 2) computation total current with ground bounce. By using fast accurate macromodeling approach,...
Emerging impulse-based ultra-wideband (UWB) technology shows strong advantages for the implementation of low-power transceivers. In this paper we propose a carrier-based UWB system that brings two distinctive over other systems: 1) lower power operation due to fact signal processing is optimally partitioned between analog and digital baseband; 2) better spectrum utilization enabling diversity multi-user systems. One core blocks in pulser serves as transmitter RF front-end template generator...
Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb analog and RF sharing same substrate. Simulations at circuit level of substrate coupling in large systems-on-chip (SoCs) do not provide necessary understanding problem. Analysis higher abstraction gives much more insight mechanisms. This paper presents physical model to estimate understand generation modem, propagation this resulting performance degradation LC tank VCOs. The proposed linearized is...
Substrate noise generated by the switching digital circuits degrades performance of analog embedded on same substrate. It is therefore important to know amount at a certain point Existing transistor-level simulation approaches based substrate model extracted from layout information are not feasible for practical size. This paper presents complete high-level methodology, which simulates large standard cell-based design using network macromodels, with one macromodel each cell. Such macromodels...
A physics-based system-level electromigration (EM) modelling platform is employed to simulate EM and its impact on the IR drop from supply voltage standard-cells for a power delivery network design in 3 nm logic node. The simulated PDN elicited high EM-tolerance. Despite voiding multiple segments, induced IR-drop increase at standard-cell level stayed below 3.3% without any catastrophic failures. Use of ruthenium rails reduced penalty system by factor ~0.6 compared with copper rails.
In a synchronous clock distribution network with zero latencies, digital circuits switch simultaneously on the edge, therefore they generate substrate noise due to sharp peaks supply current. We present novel methodology optimizing tree for less generation by using statistical single cycle current profiles computed every region taking timing constraints into account. Our is as it uses an error-driven compressed data set during optimization over number of regions specified significant...