A5076274517- Low-power high-performance VLSI design
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Advanced Memory and Neural Computing
- Thin-Film Transistor Technologies
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Ferroelectric and Negative Capacitance Devices
- 3D IC and TSV technologies
- CCD and CMOS Imaging Sensors
- VLSI and FPGA Design Techniques
- Ultra-Wideband Communications Technology
- Energy Harvesting in Wireless Networks
- Parallel Computing and Optimization Techniques
- Interconnection Networks and Systems
- Organic Electronics and Photovoltaics
- Science Education and Pedagogy
- Electromagnetic Compatibility and Noise Suppression
- Integrated Circuits and Semiconductor Failure Analysis
- Electrostatic Discharge in Electronics
- Photonic and Optical Devices
- Indoor and Outdoor Localization Technologies
KU Leuven
2016-2025
IMEC
2015-2024
VIB-KU Leuven Center for Microbiology
2016-2017
Ghent University
2016
Imec the Netherlands
2012
National Tsing Hua University
2012
Industrial Technology Research Institute
2012
Fund for Scientific Research
2007
Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically. Through silicon vias (TSVs) form an integral component of the 3-D IC technology enabling vertical interconnections in ICs. TSV resistance, inductance, and capacitance need be modeled determine their impact on performance circuit. In this paper, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</i> parameters are as...
SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase intra-die variability V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> scaling. This paper analyzes N-curve metrics compares them with commonly used static noise margin (SNM) metric defined by Seevinck. Additionally, new derived from same introduced compared traditional write-trip point definition. Analytical...
ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition [1]. New trends such as augmented reality demand always-on processing wearable devices. Yet, advanced ConvNets high rates too expensive terms of energy they require substantial data movement and billions convolution computations. Today, mobile GPU's ConvNet accelerator ASICs [2][3] only demonstrate energy-efficiencies 10's to several 100's...
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact TSV on BEOL interconnect reliability is limited, no failures have been observed. stress MOS devices causes <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Vth}$</tex></formula> shifts, further analysis required to understand their importance. Thermal hot spots in chip stacks cause...
Wireless microsensor networks, which have been the topic of intensive research in recent years, are now emerging industrial applications. An important milestone this transition has release IEEE 802.15.4 standard that specifies interoperable wireless physical and medium access control layers targeted to sensor node radios. In paper, we evaluate potential an radio for use ultra low power operating a dense network. Starting from measurements carried out on off-the-shelf radio, effective...
Forty years after the first silicon microprocessors, we demonstrate an 8-bit microprocessor made from plastic electronic technology directly on flexible foil. The operation speed is today limited to 40 instructions per second. power consumption as low 100 μW. ALU-foil operates at a supply voltage of 10 V and back-gate 50 V. can execute user-defined programs: execution multiplication two 4-bit numbers calculation moving average string incoming 6-bit numbers. To such dedicated tasks...
We report for the first time demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The TSV process is inserted between contact and M1 our reference 0.13 mum CMOS on 200 mm wafers. top die thinned down to 25 bonded landing wafer Cu-Cu thermo-compression. Both wafers contain finished at M2 evaluate impact both FEOL BEOL. results confirm no degradation performance. functionality various ring oscillator topologies that include inverters...
Dual-gate organic transistor technology is used to increase the robustness of digital circuits as illustrated by higher inverter gains and noise margins. The additional gate in functions a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -control gate. Both zero- xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> -load diode-load logic are investigated. margin increases from 1.15 V...
Abstract Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays 1–3 , image sensors 4–6 microprocessors 7–11 wearable healthcare patches 12–15 digital microfluidics 16,17 more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies a single wafer the multi-project concept enables aggregation of various CMOS chip designs within same die, TFT fabrication is currently lacking fully verified, universal...
The Internet of Things is driving extensive efforts to develop intelligent everyday objects. This requires seamless integration relatively simple electronics, for example through 'stick-on' electronics labels. We believe the future evolution this technology will be governed by Wright's Law, which was first proposed in 1936 and states that cost a product decreases with cumulative production. implies generic electronic device can tailored application-specific requirements during downstream...
Flexible low-cost RFID/NFC tags have great potential to be embedded in everyday objects providing them a unique identifier or sensor readout facilitating the Internet-of-Everything, whereby smartphone tablet is interface Internet-of-Things. The main challenge for flexible metal-oxide RFID fully comply with ISO14443-A NFC standard enable by reader handheld devices, due limited charge carrier mobility of semiconductor and multiple sources parameter variation caused roughness, temperature...
The maturity of metal-oxide thin-film transistors (TFT) highlights opportunities to develop robust and low-cost electronics on flexible stretchable substrates over large area in an industry-compatible technology. Internet-of-Everything applications with sensor nodes are driving the development analog-to-digital converters (ADCs). In this paper, a self-biased self-digital-controlled successive approximation ADC integrated references read-in circuitry together printed negative temperature...
Deep neural network (DNN) inference requires a massive amount of matrix-vector multiplications which can be computed efficiently on memory arrays in an analog fashion. This approach highly resistive devices with low resistance variability to implement DNN weight memories. We propose optimized Spin-Orbit Torque MRAM (SOT-MRAM) as Analog in-Memory Computing (AiMC) systems for inference. In SOT-MRAM the write and read path are decoupled. allows changing MTJ high levels required AiMC by tuning...
Through-silicon via (TSV) constitutes a key component interconnecting adjacent dies vertically to form 3-D integrated circuits. In this letter, we propose method exploit the TSV C-V behavior in p-silicon substrate achieve minimum capacitance during circuit operation. The nature of characteristics depends both on architecture and manufacturing process, these factors should be optimized obtain depletion desired operating voltage region. Measured demonstrate effectiveness method.
An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital is presented. modulator translates the analog input to an duty-cycle modulated signal. Next, edge locations are digitally measured using a converter (TDC). This information then processed into conventional digital The performance of this novel ADC theoretically analyzed verified with simulations. With proposed demodulation algorithm, 11-bit resolution can be obtained overcycling ratio (OCR)...
This paper presents a fully digital polar up-converter for wireless transmission in the GHz range. The system is designed to drive two class-E power amplifiers (PAs) with combiner. It uses baseband pulse width modulation (PWM) amplitude (AM), whereas phase (PM) implemented by shifting RF carrier time. Both PWM and PM are using asynchronous delay lines which allow time resolutions down 10 ps without need any reference frequencies higher than frequency. supports continuous range of from 946...