A5002340330- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- 3D IC and TSV technologies
- Interconnection Networks and Systems
- Additive Manufacturing and 3D Printing Technologies
- Mediterranean and Iberian flora and fauna
- Neuroinflammation and Neurodegeneration Mechanisms
- Barrier Structure and Function Studies
- Electronic Packaging and Soldering Technologies
- Real-Time Systems Scheduling
- Semiconductor materials and devices
- Neuroscience and Neuropharmacology Research
- Memory and Neural Mechanisms
- Plant and animal studies
- Horticultural and Viticultural Research
- Low-power high-performance VLSI design
- Neurological Disease Mechanisms and Treatments
- Entomological Studies and Ecology
- Plant Physiology and Cultivation Studies
- Insect and Arachnid Ecology and Behavior
- Electrostatic Discharge in Electronics
- Botany and Plant Ecology Studies
- Advanced Data Storage Technologies
- Diptera species taxonomy and behavior
- Sleep and Wakefulness Research
Université Claude Bernard Lyon 1
2018-2025
Centre de Recherche en Neurosciences de Lyon
2025
Inserm
2024-2025
University of Arizona
2023
University of California, Los Angeles
2023
Duke-NUS Medical School
2023
Experimental Medicine and Biology Institute
2023
Consejo Nacional de Investigaciones Científicas y Técnicas
2023
Centre National de la Recherche Scientifique
2019-2020
Centre de Recherches sur la Cognition Animale
2019-2020
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact TSV on BEOL interconnect reliability is limited, no failures have been observed. stress MOS devices causes <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm Vth}$</tex></formula> shifts, further analysis required to understand their importance. Thermal hot spots in chip stacks cause...
An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely operating systems to map these the architecture. However, today's embedded abstract away precise architectural details platform. As a consequence, they cannot exploit energy efficiency scratchpad memories. We present in this paper novel integrated hardware/software solution support memories at high abstraction level. hardware alleviate transfer cost from/to...
As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by through silicon vias (TSV) is one of key constraints in flow that must be controlled order preserve integrity front end devices. For first time an extended comprehensive study given for single- arrayed TSVs its impact on both analog digital FEOL devices circuits. This work provides complete...
This paper addresses the problem of mapping an application, which is highly dynamic in future, onto aheterogeneous multiprocessor platform energy efficient way. A two-phase scheduling method used for that purpose. By exploring Pareto curves and scenarios generated at design time, run-time scheduler can easily find a good very low overhead, satisfying system constraints minimizing consumption. real-life example from 3D quality service kernel to show effectiveness our method.
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating "hot spots" on die. As a result, performance, reliability consumption of system degrade. To avoid these spots", "temperature-aware" design has become must. For low-power embedded though, it is not clear whether similar thermal problems occur. These have very different characteristics from ones: they consume hundred times less...
Stacking memory with 3D chip integration technology could provide the much needed bandwidth and density for mobile applications at low power. The contribution of this paper is to review desired attributes a stackable from system aspects discuss its implementation challenges.
Microglia exhibit diverse morphologies reflecting environmental conditions, maturity or functional states. Thus, morphological characterization provides important information to understand microglial roles and functions. Most recent analysis relies on classifying cells based parameters. However, this classification may lack biological relevance, as represent a continuum rather than distinct, separate groups, do not correspond mathematically defined, clusters irrelevant of function. Instead,...
Interactions among brain areas are essential to most cognitive functions. Neuronal interactions between these depend on the modulation of synaptic strength. However, this remains poorly understood. We recorded evoked responses at four hippocampal pathways in freely moving male rats across 24 hours. show that strength oscillates with a very slow periodicity and correlates durations vigilance states. A model based hypnogram data one pathway was able predict evolution pathways, except one....
Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms size, bandwidth power consumption. The existing solution for the bottle-neck is to increase amount on-chip memory. However, this becoming prohibitively expensive, allowing 3D stacked DRAM become an interesting alternative applications. In paper, we examine power/performance benefits three different scenarios. Our high-level Through Silicon Via (TSV) models have...
3D-TSV technologies promise increased system integration at lower cost and reduced footprint. One of the most likely applications 3D technology is DRAM-on-logic. Thermal management issues are considered one potentially showstoppers for 3D-integration. In this paper, we present a thermal experimental modeling characterization packaged DRAM on logic stack. The die stacked to thinned (25μm) using CuSn microbumps. For dedicated chip with integrated heaters sensors used. impact hot spot...
The power density in high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating 'hot spots' on die. As a result, performance, reliability consumption of system degrade. To avoid these spots', 'temperature-aware' design has become must. For low-power embedded though, it is not clear whether similar thermal problems occur. These have very different characteristics from ones: e.g., they consume 100 times less...
This paper presents a high-frequency modeling method of direct current motor armatures dedicated to low-voltage automotive applications. The proposed model is based on behavioral approach, which permits reproduce impedance measurements. It takes into account some physical features and phenomena related the armature. influence skin effect in windings, magnetic field penetration core, armature manufacturing systematic error evolution considered with this model. was first developed from that...
3D stacking of dies is a promising technique to allow miniaturization and performance enhancement electronic systems. The complexity the interconnection structures, combined with reduced thermal spreading in thinned poorly thermally conductive adhesives complicate behavior stacked die structure. same dissipation will lead higher temperatures more pronounced temperature peak package compared single package. Therefore, 3D-IC needs be studied thoroughly. In this paper, steady state transient...
Silicon substrates can be strategically isolated or unified among tiers in a through-silicon-via (TSV)-based 3-D integrated circuit (IC) structure, for the suppression of intertier substrate noise coupling reduction grounding impedance silicon as whole, respectively. A two-tier IC demonstrator 130-nm CMOS technology was successfully tested and analyzed with respect to intra coupling. Each tier stack includes digital source circuits (NSs) monitors, embodies in-place measurements An equivalent...
Abstract The superiority of spaced over massed learning is an established fact in the formation long-term memories (LTM). Here we addressed cellular processes and temporal demands this phenomenon using a weak spatial object recognition (wSOR) training, which induces short-term (STM) but not LTM. We observed SOR-LTM promotion when two identical wSOR training sessions were by inter-trial interval (ITI) ranging from 15 min to 7 h, consistently with training. promoting effect was dependent on...
Besides the stress around Cu TSV's, also induced by microbumps is a main contributor to transistor level stress. For complete and successful deployment of 3D IC all effects generating have be addressed. Therefore, this work quantifies its associated with their interaction underfill material in stacks using combined experimental theoretical approach. We report on generated backside affecting FETs through thinned silicon die thin caused stacking. find that FET current shifts reach over 40% due...