An ever increasing number of dynamic interactive applications are implemented on portable consumer electronics. Designers depend largely operating systems to map these the architecture. However, today's embedded abstract away precise architectural details platform. As a consequence, they cannot exploit energy efficiency scratchpad memories. We present in this paper novel integrated hardware/software solution support memories at high abstraction level. hardware alleviate transfer cost from/to...

Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations bus-based solutions. NoC can have regular or ad hoc topologies, functional validation is essential to assess their correctness performance. In this paper, we present flexible emulation environment implemented an FPGA suitable explore, evaluate compare wide range solutions with very...

With the growing complexity in consumer embedded products and improvements process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread.These new systems are complex to design as they must execute multiple applications (e.g.video processing, 3D games), while meeting additional constraints (e.g.energy consumption or time-to-market).Moreover, rise of temperature die for MPSoC components can seriously affect their final performance reliability.Therefore,...

New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for the consumer electronics market. MPSoCs are complex to design, they must execute multiple applications (games, video) while meeting additional design constraints (energy consumption, time-to-market). Moreover, rise of temperature in die can seriously affect their final performance and reliability. In this article, we present new hardware-software emulation framework that allows designers complete...

Speculative functional units (SFUs) are arithmetic that operate using a predictor for the carry signal. The prediction helps to shorten critical path of unit. average case performance these is determined by hit rate prediction. In mispredictions, SFUs need be coordinated datapath control mechanism perform corrections and maintain in correct state. Devising correcting mispredictions without adversely impacting overall most important challenge. this paper, we present techniques designing...

New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they heavily rely on Dynamic Memory (DM) due to the unpredictability of input data (e.g., 3D streams features) system behavior number running concurrently defined by user). Within this context, consistent design methodologies can tackle efficiently complex DM these are in great need. In article, we present a new methodology allows custom...

Addition is the key arithmetic operation in most digital circuits and processors. Therefore, their performance other parameters, such as area power consumption, are highly dependent on adders' features. In this paper, we present multispeculation a way of increasing with low penalty. our proposed design, dividing an adder into several fragments predicting carry-in each fragment enables computing every addition two very short cycles at most, 99% or higher probability. Furthermore, based...

Embedded systems are evolving from traditional, stand-alone devices to that participate in Internet activity. The days of simple, manifest embedded software [e.g. a simple finite-impulse response (FIR) algorithm on digital signal processor (DSP] over. Complex, nonmanifest code, executed variety platforms distributed manner, characterizes next generation software. One dominant niche, which we concentrate on, is embedded, multimedia need present map large scale, dynamic, onto an system...

Current systems-on-chip execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations bus-based solutions. NoCs can have regular or ad hoc topologies, functional validation is essential to assess their correctness performance. In this paper, we present flexible emulation environment implemented an FPGA suitable explore, evaluate compare wide range NoC solutions with very...

Conventional scheduling algorithms try to balance the number of operations every different type executed per cycle. However, in most cases, a uniform distribution is not reachable, and thus, some hardware (HW) waste appears. This situation becomes worse when heterogeneous specifications (those formed by with data formats widths) are synthesized. Our proposal an innovative bit-level algorithm able minimize this HW waste. In order obtain distributions computational cost among cycles, it...

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and cooling. Hence, mechanisms efficiently evaluate effectiveness advanced thermal-aware operating-system (OS) strategies (e.g. task migration) onto available MPSoC hardware are needed. In this paper, we propose a new OS emulation framework that...

With the growing complexity in consumer embedded products and improvements process technology, multiprocessor system-on-chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple real-time applications (e.g. video processing, or videogames), while meeting several additional constraints energy consumption time-to-market). Therefore, mechanisms efficiently explore different possible HW-SW interactions complete MPSoC great need....

New portable consumer embedded devices must execute multimedia and wireless network applications that demand extensive memory footprint. Moreover, they heavily rely on dynamic (DM) due to the unpredictability of input data (e.g. 3D streams features) system behaviour number running concurrently defined by user). Within this context, consistent design methodologies can tackle efficiently complex DM these are in great need. In paper, we present a new methodology allows custom management...

The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space High-Level Synthesis (HLS).Nevertheless their use is restricted to only few operators in datapaths because number cases control grows exponentially.In this work an instance VLFUs described, and based on its structure, average latency tree structures improved.Multispeculative (MSFUs) are arithmetic that operate using several predictors for carry signal.In spite utilizing more than a predictor,...

In this paper, we propose a new approach to design convenient dynamic memory management subsystems, profiting from the multiple levels. It analyzes logical phases involved in modem applications effectively distribute dynamically allocated data among multi-level hierarchies present embedded devices. We assess effectiveness of proposed for three representative real-life case studies application domains (i.e., network and 3D rendering applications) ported systems. The results accomplished with...

This paper justifies the use of estimation and prediction carries to increase performance functional units built with replication full adders while keeping a low area penalization. Adders multipliers are most representative modules in this group units. The these design techniques allows implementation improvements ranging from 20% 50% only an overheads around 5%. These suitable for asynchronous circuits but they could also be introduced synchronous speculative techniques. basic idea consists...

Speculative Functional Units (SFUs) enable a new execution paradigm for High Level Synthesis (HLS). SFUs are arithmetic functional units that operate using predictor the carry signal, which reduces critical path delay. The performance of these is determined by success in prediction value, i.e. hit rate prediction. Hence reduce at low cost, but they cannot be used HLS with current techniques. In order to use them, it necessary include hardware support recover from mispredictions signals. this...

New applications in embedded systems are becoming increasingly dynamic. In addition to increased dynamism, they have massive data storage needs. Therefore, rely heavily on dynamic, run-time memory allocation. The design and configuration of a dynamic allocation subsystem requires big effort, without always achieving the desired results. this paper, we propose fully automated exploration configurations. These configurations fine tuned specific needs with use number parameters. We assess...

This paper presents a heuristic scheduling algorithm for heterogeneous specifications, those formed by operations of different types and widths. The extracts the common operative kernel operations, binds afterwards to cycles with aim distributing uniformly number bits calculated per cycle. In consequence, may be fragmented executed during set non-necessarily consecutive cycles, over several linked simple hardware resources. proposed algorithm, in combination allocation algorithms able...

The long computation times required to simulate complete aircraft configurations remain as the main bottleneck in design flow of new structures for aeronautics industry. In this paper, novel application specific hardware conjunction with conventional processors accelerate Computational fluid dynamics is explored. First, some general facts about application-specific are presented, placing focus on feasibility development modules (FPGAs based) acceleration most time-consuming algorithms...

The information about the run-time behavior of software applications is crucial for enabling system level optimizations embedded systems. This Software Metadata especially important today, because several complex multi-threaded are mapped on memory a single system. Each thread triggered at by different input events that can not be predicted design-time. New methods and tools needed to automatically profile analyze dynamic data access simultaneously executing threads in order enable transfer...