A5019510660- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Semiconductor materials and interfaces
- Nanowire Synthesis and Applications
- Silicon Nanostructures and Photoluminescence
- Advanced Memory and Neural Computing
- Semiconductor Quantum Structures and Devices
- VLSI and Analog Circuit Testing
- Advanced Electron Microscopy Techniques and Applications
- Thin-Film Transistor Technologies
- Silicon and Solar Cell Technologies
- Quantum and electron transport phenomena
- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- Radiation Effects in Electronics
- Silicon Carbide Semiconductor Technologies
- Copper Interconnects and Reliability
- Advanced Surface Polishing Techniques
- Real-Time Systems Scheduling
- Electromagnetic Compatibility and Noise Suppression
- Advanced Battery Technologies Research
IMEC
2015-2024
KU Leuven
2017-2020
Micron (United States)
2013-2015
Micron (Italy)
2012
STMicroelectronics (Czechia)
2008
University of Modena and Reggio Emilia
2006-2007
In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs nanowire (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable at same channel cross section. On top of that, RO evaluated by taking into account electrostatics, parasitic components, layout configurations. NSH-FETs an advantage in drive current the NSH...
This article reviews the status, challenges, and perspective of 1T-1C dynamic random access memory (DRAM) chip. The basic principles DRAM are presented, introducing key functional aspects structure modern devices. We present most relevant historical trends for different modules chip, such as device storage element, reviewing some technological challenges faced by industry to guarantee shrinking imposed economic law. recent solutions introduced in devices critical elements presented. Finally,...
Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify Very-Large-Scale Integrated (VLSI) circuit-level CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs gate-all-around nanowires/nanosheets]. We use industry-practice physical designs VLSI processor cores in future nodes with millions...
We report on CMOS-integrated vertically stacked gate-all-around (GAA) Si nanowire (NW) MOSFETs with in-situ doped source-drain stressors and dual work function metal gates. demonstrate that oxidation-induced SiGe/Si fin deformation by STI densification is effectively suppressed a SiN liner. This protection improves the controllability of formation. In addition, highly-selective nano-wire release inner spacer cavity formation without re-flow are demonstrated. Finally, for first time we...
In this paper, we show how 5.5 tracks standard cells can be enabled at gate pitch 42 nm and metal 21 achieve 60% active power reduction from the 7nm node. A device downselection methodology driven by performance targets is introduced. This method demonstrates that three stacked nanosheets of 20 width are competitive with FinFETs made two fins while relaxing constraints on layout design rules.
To compensate for expected gate pitch scaling slowdown below 42nm, several boosters are needed to reduce the logic standard cell height (CH). However, limited benefits can be achieved using FinFET and Gate all around (GAA) nanosheets (NSHs) due integration limits in achieving tight PMOS NMOS (PN) separation. Therefore, a novel forksheet (FSH) device architecture is proposed extremely scaled PN space additional processing complexity. The FSH achieves 10% frequency increase at iso-power 24%...
With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews latest trends advances enable scaling. Dimensional scaling, enabled by EUV lithography, will continue with multi-patterning. Higher costs multi-patterning be mitigated high (0.55) numerical aperture (NA) simplifying patterning potentially leading higher yield. Logic standard cell scaling below 6-track (6T) adequate...
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A CFET process is cost effective compared to a sequential process. The small N/P separation in results lower parasitics and higher performance gains. In this paper, fabrication flow, we demonstrate functional PMOS FinFET bottom devices NMOS nanosheet FET top devices. Process development all critical modules enable these are presented. Monolithic scheme...
By optimizing design rules, layout, devices and parasitics, we show how 5 Tracks standard cells with one fin can be enabled. This reduces area by 16% without pitch scaling provides 34% energy gain from 6T cells. The loss in speed of 15% recovered different front-end solutions. Air gap spacers are the most efficient booster provide an extra energy. Lateral Nanowires compete FinFETs 12% if tight vertical 10 nm between wires achieved.
The increased complexity of CMOS transistor processing has led to limited scaling high density SRAM cell at advanced technology nodes. STT-MRAM appears be a promising candidate for replacing last level caches (LLC). This paper addresses design co-optimization (DTCO) and analyzes its viability as LLC (compared SRAM) the performance computing (HPC) domain (while maintaining constraint occupying merely 43.3% macro area identical capacities). is first study that breaks down power, (PPA)...
The technology of buried power rails and back-side delivery has been proposed for future scaling enablement, beyond the 5nm node. This paper studies CPU design implications in context these technologies. Employing standard VLSI flows sign-off techniques, we benchmark designs options using Arm Cortex-A53 at an imec 3nm DC AC analyses resulting networks are presented various with (with front-side delivery) compared to conventional without rails. It is shown that can improve worst-case IR drop...
Driven by concerns on climate change, resources depletion, local and global pollution, sustainability is becoming an integral component of business regulations. The progress Design Technology Co- Optimization (DTCO) methodologies tools, building transversal knowledge from manufacturing to design, provides opportunity develop a framework for early assessments logic technologies. Environmental scores can be derived together with the established Power, Performance, Area, Cost (PPAC) metrics. To...
We present a method to reduce the size and improve crystal quality of freestanding nanowires grown by electron beam induced deposition from platinum metal organic precursor in dual system. By horizontal growth subsequent irradiation transmission microscope, sub-10-nm polycrystalline have been obtained. A combined microscopy–electron energy loss analysis has shown that amorphous carbon, mixed nanocrystalline as-deposited material, is removed wires during irradiation. The same treatment...
This paper discusses SRAM scaling beyond the 5nm technology node and highlights fundamental limits due to FinFET Gate all-around (GAA) technology. To compensate for expected gate pitch slowdown below 42nm, several boosters are needed reduce cell height. However, limited benefits can be achieved in GAA Therefore, a novel vertically stacked lateral nanosheet architecture using forked structure is proposed showing superior performance area compared devices. Moreover, additional processing...
The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry-relevant solutions for FF GAA-NW Si high-mobility devices, with multiple processing options. Considerations managing SH in future technologies are provided.
Superior electrostatic control of 2D-FETs enables continued logic power-performance-area (PPA) scaling beyond the 2nm node. Here, we show that WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based 2D devices give ~40% inverter performance boost against Si at imec node, using a process-aware DTCO approach. The is conducted based on an ab-initio calibrated, physical compact model while area contacted gate pitch scaling. Side...
This letter proposes for the first time buried powered static random-access memory (SRAM) to achieve enhanced write margin and performance in advanced CMOS technology nodes. The power rail (BPR) SRAM is silicon verified. BPR helps lower bitline wordline resistance by relaxing metal width circuits thereby enhances performance. proposed provides up 340 mV 30.6% improvement read speed, respectively, as compared its conventional counterpart without incurring any area penalty a hardware...
Buried power rail (BPR) and back-side delivery grid have been proposed as solutions to scaling challenges that arise beyond the 5-nm technology node, mainly lower IR drop further shrink area. This article demonstrates a holistic evaluation of this its variants at microprocessor level. is carried out by taking an Arm Cortex-A53 design through standard-VLSI physical implementation flow on Imec’s iN6 equivalent industry 3-nm which features buried technology. The power, performance, area,...
This work investigates the variability effects on threshold voltage distribution of deca-nanometer NAND Flash memories. Different sources have been considered, evaluating their impact neutral, programmed and erased distributions. A compact model that is able to account for array performance reliability presented used. Monte Carlo simulations employed analyze contributions when technology nodes scale down compare intrinsic with electron injection statistical fluctuations. good agreement...
In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack based on HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> coupled Al O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping for pMOS devices, TiN/Mg/TiN together As ion implantation nMOS. It...
The targeted N3 technology node at IMEC is being redefined with respect to the poly pitch, as compared previous definitions [1,2]. overall industry trend of pitch scaling slowing down, due difficulties in keeping pace device performance and yield issues. However, metal continues scale which implies that direct will not lead most optimum scaling. Therefore, Standard Cell (SDC) track height reduction a knob can be used achieve advances preserve Moore's law. Here we present some options for...
The increased metal resistance degrades both the performance and write margin of SRAM circuits in sub-10nm nodes. This paper utilizes buried power distribution as ability booster 3nm node. BPR-SRAM offers up to 34.5% read speed 498.6mV improvement over conventional SRAM. Gem5 system simulator predicts 28.2% gain with server-processor having L2 L3 cache compared baseline.
This paper describes a defect-centric based compact modeling methodology for time-dependent threshold voltage variability (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ), induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN). A Verilog-A model wrapper is used to implement shift adding variable source at the gate of core device model. allows incorporate all BTI RTN related electrostatics kinetics in standard...
Deep insights into the Off-State Stress (OSS) degradation mechanism on p-MOSFETs with High-K/Metal Gate technology are presented in this paper. Large subthreshold slope degradation, or positive Vth shift is observed high, low devices, where both phenomena impact off current degradation. The OSS pMOS generated by (1) hot carrier generation close to drain junction ionization, then (2) electron injection oxide bulk defects, and (3) Si/oxide interface Both TCAD simulations measurement...