A5061843047- Carbon Nanotubes in Composites
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Graphene research and applications
- Analog and Mixed-Signal Circuit Design
- Ferroelectric and Negative Capacitance Devices
- CCD and CMOS Imaging Sensors
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Quantum-Dot Cellular Automata
- 3D IC and TSV technologies
- Photonic and Optical Devices
- Parallel Computing and Optimization Techniques
- Mechanical and Optical Resonators
- Nanowire Synthesis and Applications
- Interconnection Networks and Systems
- Advanced MEMS and NEMS Technologies
- Photoreceptor and optogenetics research
- Integrated Circuits and Semiconductor Failure Analysis
- Electrochemical Analysis and Applications
- Nanotechnology research and applications
- ZnO doping and properties
- Particle Detector Development and Performance
- Advancements in PLL and VCO Technologies
Analog Devices (United States)
2023-2025
Massachusetts Institute of Technology
2017-2025
IIT@MIT
2020-2023
Tokyo Electron (Japan)
2023
Applied Materials (Germany)
2023
Imec the Netherlands
2023
MediaTek (China)
2023
University of California, Los Angeles
2023
Tokyo Institute of Technology
2023
Samsung (South Korea)
2023
Next-generation information technologies will process unprecedented amounts of loosely structured data that overwhelm existing computing systems. N3XT improves the energy efficiency abundant-data applications 1,000-fold by using new logic and memory technologies, 3D integration with fine-grained connectivity, architectures for computation immersed in memory.
Patterns composed of solvent wetting and dewetting regions promote lateral confinement solution-sheared lattice-strained TIPS-pentacene crystals. This causes aligned crystal growth, the smallest patterns 0.5 μm wide promotes formation highly strained, aligned, single-crystalline with mobility as high 2.7 cm2 V−1 s−1.
We demonstrate monolithic 3D integration of logic and memory in arbitrary vertical stacking order with the ability to use conventional inter-layer vias connect between any layers IC. experimentally show 4 vertically-stacked (logic layer followed by two another layer), enabled traditional silicon-FETs (on bottom-most layer) low-processing-temperature emerging nanotechnologies: metal-oxide resistive random-access (RRAM), carbon nanotube-FETs (CNFETs). As a demonstration, we routing element...
We demonstrate an end-to-end brain-inspired hyperdimensional (HD) computing nanosystem, effective for cognitive tasks such as language recognition, using heterogeneous integration of multiple emerging nanotechnologies. It uses monolithic 3D carbon nanotube field-effect transistors (CNFETs, logic technology with significant energy-delay product (EDP) benefit vs. silicon CMOS [1]) and Resistive RAM (RRAM, memory that promises dense non-volatile analog storage [2]). Due to their low fabrication...
Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify Very-Large-Scale Integrated (VLSI) circuit-level CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs gate-all-around nanowires/nanosheets]. We use industry-practice physical designs VLSI processor cores in future nodes with millions...
The world's appetite for analyzing massive amounts of structured and unstructured data has grown dramatically. computational demands these abundant-data applications, such as deep learning, far exceed the capabilities today's computing systems are unlikely to be met with isolated improvements in transistor or memory technologies, integrated circuit architectures alone. To achieve unprecedented functionality, speed, energy efficiency, one must create transformative nanosystems whose based on...
The field of machine learning is witnessing rapid advances along several fronts: new models, algorithms utilizing these hardware architectures for algorithms, and technologies creating energy-efficient implementations such architectures. Hyperdimensional (HD) computing represents one model. Emerging nanotechnologies, as carbon nanotube field-effect transistors (CNFETs), resistive random-access memory (RRAM), their monolithic 3D integration, enable energyand area-efficient HD Such efficient...
Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, metric performance and energy efficiency, compared silicon-based circuits. However, due substantial imperfections inherent with CNTs, the promise CNFETs has yet be fully realized. Techniques overcome these have yielded results, but thus far only at large nodes (1 μm device size). Here we demonstrate first very scale...
We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability broad range of 1D 2D nanomaterials beyond nanotubes. The Measurement enables quantification (density, energy level, spatial distribution) charged traps responsible hysteresis. A physics-based model charge trapping process transistor is presented experimentally validated using Measurement. Leveraging...
We present a technique to increase carbon nanotube (CNT) density beyond the as-grown CNT density. perform multiple transfers, whereby we transfer CNTs from several growth wafers onto same target surface, thereby linearly increasing on substrate. This process, called of nanotubes through sacrificial layers, is highly scalable, and demonstrate linear scaling up 5 transfers. also that this results in an ideal drain−source currents field effect transistors (CNFETs). Experimental can be improved...
Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new innovative interface architectures technologies. Carbon nanotube FETs (CNFETs) excellent candidates further reduction, CNFET-based digital circuits projected to achieve an order magnitude improvement energy-delay product compared with silicon-CMOS at highly scaled technology nodes. However, carbon nanotubes (CNTs) inherently subject...
While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As is caused by traps surrounding the CNTs, previous works have shown that clean interfaces are free of important to minimize hysteresis. Our findings on sources physics in CNFETs enabled us understand influence gate dielectric scaling To begin with, we validate through simulations how thickness results...
Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CMOS process must be robust ( e.g., air-stable), tunable ability to control threshold voltages), silicon compatible (to integrate within existing manufacturing facilities flows). Despite many efforts, such CNT...
Carbon nanotube (CNT) field-effect transistors (CNFETs) promise significant energy efficiency benefits versus today's silicon-based FETs. Yet despite this promise, complementary (CMOS) CNFET analog circuitry has never been experimentally demonstrated. Here we show the first reported demonstration of full CMOS circuits. For characterization, fabricate building block circuits: multiple instances two-stage op-amps. These op-amps achieve gain >700 (maximum derivative output voltage with respect...
Monolithic three-dimensional (3D) integration enables revolutionary digital system architectures of computation immersed in memory. Vertically-stacked layers logic circuits and memories, with nano-scale inter-layer vias (with the same pitch dimensions as tight-pitched metal layer vias), provide massive connectivity between layers. The are orders magnitude denser than conventional through silicon (TSVs). Such can achieve significant performance energy efficiency benefits compared to today's...
The demands of future applications in computing (from self-driving cars to bioinformatics) overwhelm the projected capabilities current electronic systems. need process unprecedented amounts loosely structured data is driving push for ultradense and fine-grained integration traditionally off-chip components (e.g., sensors, memories) with energy-efficient computation units—all within a single chip. Monolithic 3-D leading approach building such systems, as it naturally enables connectivity...
We demonstrate carbon nanotube (CNT) field-effect transistors (CNFETs) with the highest current drive (per unit layout width) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> to-date (>100 µA/µm at 400 nm channel length and 1V V <inf xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> ), while simultaneously achieving high I xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> /I xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>...
Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) inherently subject to variations that reduce circuit yield, increase susceptibility noise, and severely degrade their anticipated energy speed benefits. Joint exploration optimization of CNT processing options CNFET design required overcome this outstanding challenge. Unfortunately, existing approaches...
As continued scaling of silicon FETs grows increasingly challenging, alternative paths for improving digital system energy efficiency are being pursued. These include replacing the transistor channel with emerging nanomaterials (such as carbon nanotubes), well utilizing negative capacitance effects in ferroelectric materials FET gate stack, e.g., to improve sub-threshold slope beyond 60 mV/decade limit. However, which path provides largest benefits—and whether these multiple can be combined...
We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). 1 kbit (1024) 6 transistor (6T) SRAM fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), all 1024 cells functioning correctly without any per-unit customization. Moreover, we show demonstration of CNFET CMOS 10T cells, capable operating at highly scaled voltages down to 300 mV. characterize...
While carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the performance and energy efficiency of digital systems beyond limitations silicon CMOS, presence metallic CNTs (m-CNTs) remains a major challenge. Existing techniques for removing m-CNTs are inadequate, as they face one or more following scalability challenges: scaling large circuits (≥99.99% must be removed without inadvertently semiconducting CNTs, s-CNTs), short channel lengths (for highly-scaled contacted...