A5108237344- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor Quantum Structures and Devices
- Silicon and Solar Cell Technologies
- Semiconductor materials and interfaces
- Nanowire Synthesis and Applications
- Thin-Film Transistor Technologies
- Photonic and Optical Devices
- Silicon Nanostructures and Photoluminescence
- 3D IC and TSV technologies
- Advanced Surface Polishing Techniques
- Silicon Carbide Semiconductor Technologies
- Copper Interconnects and Reliability
- Semiconductor Lasers and Optical Devices
- Electronic and Structural Properties of Oxides
- Advancements in Photolithography Techniques
- Radiation Effects in Electronics
- Ferroelectric and Piezoelectric Materials
- Low-power high-performance VLSI design
- Metal and Thin Film Mechanics
- VLSI and Analog Circuit Testing
- ZnO doping and properties
IMEC
2020-2024
GlobalFoundries (United States)
2013-2019
GlobalFoundries (Germany)
2017
Motorola (United States)
1999-2004
Massachusetts Institute of Technology
1996-1999
IIT@MIT
1997-1999
Purdue University West Lafayette
1994-1995
A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This has allowed us to grow a relaxed buffer 100% without the increase density normally observed thick structures. sample been characterized by transmission electron microscopy, etch-pit density, atomic force Nomarski optical triple-axis x-ray diffraction. Compared other buffers which CMP was not implemented, this exhibits improvements surface...
With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews latest trends advances enable scaling. Dimensional scaling, enabled by EUV lithography, will continue with multi-patterning. Higher costs multi-patterning be mitigated high (0.55) numerical aperture (NA) simplifying patterning potentially leading higher yield. Logic standard cell scaling below 6-track (6T) adequate...
The defect structure in relaxed graded Ge/GexSi1−x/Si structures grown on (001) exact and off-cut substrates using ultra-high vacuum chemical vapor deposition was characterized transmission electron microscopy (TEM), atomic force microscopy, beam induced current. samples showed a remarkable improvement surface roughness dislocation pile-up densities. By applying both blocking criterion to Si-Ge/Si(001) structures, we can predict the formation of pile-ups structures. Nonparallel misfit...
The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated photodiodes a graded optimized relaxed SiGe buffer Si. dark current in the mesa diodes, Js=0.15 mA/cm2, close to theoretical reverse saturation and record low diodes Si substrates. Capacitance measurements indicate that detectors are capable operating at high frequencies (2.35 GHz). exhibit an external quantum efficiency η=12.6% λ=1.3 μm...
Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions 14-nm FinFETs. Minimal radiation-induced voltage shift across a variety transistor types is observed. Off-state leakage current nMOSFET transistors exhibits strong gate dependence, indicating electrostatic control sub-fin region corresponding parasitic conduction path largest concern for radiation hardness in FinFET technology. The high-...
Relaxed SiGe thin films are used as templates to control the nucleation of three-dimensional Ge islands on Si(100) substrates. Using relaxed template, form a rectangular array with all located exclusively above intersections dislocations. The registration is lost when growth temperature lowered 300 °C, and coverage decreased 0.4 nm.
We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. epi patterning 30nm vertical N-P space high-aspect-ratio contact formation are successfully demonstrated. Functional devices excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) reported devices, both N- PMOS. Middle dielectric isolation (MDI) by SiGe replacement processing is introduced as...
Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin (W) on logic SRAM device characteristics. TCAD analysis used understand impact gate length (Lg)scaling along with optimize AC performance. In this paper, W was scaled from 8nm 1.6nm. It found that there a critical (Wc)at ~4nm. W>Wc region, due better narrower fin, drain-induced barrier lowering (DIBL), DC performance Vt...
Under typical growth conditions, strain levels greater than or equal to 10−4 are shown influence thin film surface morphology and relaxation pathways. Misfit threading dislocations in relaxed heterostructures produce long wavelength undulations on the shallow depressions, respectively. Threading dislocation densities ∼105–106 cm−2 must be due increased impediments motion, which turn originate from effect of misfit morphology. origin strain-induced features can identified by recognizing...
The epitaxial growth of GaAs on Si substrates through the use a Ge/graded Si1−xGex/Si buffer layer would allow monolithic integration GaAs-based opto-electronics with microelectronics. As an initial step toward this goal, study examines factors which influence quality by molecular beam epitaxy (MBE) bulk Ge substrates. Key findings include need for smoothing cap deposited in MBE chamber, significant detrimental effect overpressure resultant crystalline quality, and efficiency very thin (∼3...
Thin strained Si layers grown on SiGe graded to 20% Ge were studied for resistance relaxation. It was observed that in the presence of ∼105/cm2 threading dislocations from underlying layers, barrier misfit dislocation formation is sufficiently reduced induce relaxation even when layer thickness less than predicted critical thickness. Raman spectroscopy revealed elastic strain accumulation uniform a significant contributor cap layers. Upon annealing, thermal mismatch causes relax further, but...
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.124 . access stability write margin are significantly improved through a 50% Vt mismatch reduction, thanks HK-MG T <sub xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> scaling. Cell read current is increased 70% over Poly-SiON process. Ultra dense cell...
Forksheet devices have been recently proposed to further reduce the n-to-p spacing/footprint of transistors on wafer. In this work, we report a systematic comparison DC performance Forksheets and Nanosheets (with relevant dimensions 23nm width 7nm thickness) co-integrated same wafers. It is shown that short channel control transport properties (from Room Temperature up 125°C) are comparable down LG=22nm. We also show gate stack reliability does not suffer from SiN deposition etch back...
Recent advances in the understanding and control of threading dislocations substantially relaxed SiGe buffer layers on Si are presented. A model for dislocation flow graded buffers is used to determine potential lower limit density buffers. Greater densities than expected from seen alloys with final concentrations greater 50%. We show that culprits higher pile-ups. Observation early development pile-ups confirms inhomogeneous misfit form regions more severe crosshatch surface impede flow. By...
Monolithic 3D IC (M3D) shows degradation in performance compared to 2D due the restricted thermal budget during fabrication of sequential device layers. A transistor-level (TR-L) partitioning design is used M3D mitigate this degradation. Silicon validated 14nm FinFET data and models are a device-to-system evaluation compare TR-L partitioned M3D's (TR-L M3D) against conventional gate-level (G-L) as well standard IC. Extensive cell-level system-level evaluation, including various interconnect...
First microprocessor released to the market in 1971 was consisting of 2300 transistors. Following Moore's law less than five decades later consumer electronic chips consist billions transistor reaching densities as much 100 million transistors square millimeter Several times past it predicted that technological barriers would slow or even stop CMOS technology scaling trend. Despite these predictions, monetary benefit growth has been driving massive research and pathways have Lays found...
Continuous process-level and system-level innovation has driven Moore's Law scaling for the last fifty years, will continue to do so in next decades. In two decades, there been an acceleration of new materials devices into semiconductor manufacturing, such as low-k, strained Si, high-k, FinFET, order process cost scaling. At same time, ever increasing component integration on SoCs further scaling, allowing current mobile era take shape. decade, focus SoC be patterning low-resistance side,...
Epitaxy growth loading effect—the rate difference between device macros due to their local open ratio difference—is an important consideration for design and thus process optimization. A poor leads performance delta across macros. For eSiGe on FinFETs, we found that optimized FinFETs saturates as the diamond pins at fin top surface fin-sidewall-spacer (FSS). The size measured by lateral CD does not increase with deposition time, but it linearly correlates cavity depth FSS pushdown. In...
Fin-based analog, passive, RF and ESD devices have serious performance challenges, such as poor ideality, higher leakage, low breakdown voltage (BV) of diodes, BJTs with mismatch, weak re-surf action drain current(I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> /μm) Laterally diffused MOS (LDMOS), degraded 1/f noise analog CMOS, etc. Innovative solutions which maintain process simplicity cost are described in this paper. These new...
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. enables >10% area reduction including 7.5T library 16% power at fixed frequency or 15% performance given leakage 14LPP comparable reliability yield. In addition, SRAMs benefit from 30% the same Iread. extends 14nm compelling scaling.
A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents sneak current cross-point array, therefore no need for select transistor each cell. Thus enables smallest reported area measuring 0.036 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Elevated source drain (ESD) structure in deep submicron metal oxide semiconductor field effect transistors (MOSFETs) can help reduce parasitic series resistance and simultaneously achieve shallow contacting junctions to minimize short channel effects. A self-aligned ESD conventional complimentary metal–oxide–semiconductor processing be achieved using silicon selective epitaxial growth (SEG). robust low thermal budget high quality SEG process a commercial rapid chemical vapor deposition...