A5076455589- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Stellar, planetary, and galactic studies
- Adaptive optics and wavefront sensing
- Infrared Target Detection Methodologies
- Gamma-ray bursts and supernovae
- Astronomical Observations and Instrumentation
- Low-power high-performance VLSI design
- Astronomy and Astrophysical Research
- Ferroelectric and Negative Capacitance Devices
- Galaxies: Formation, Evolution, Phenomena
- Astrophysics and Cosmic Phenomena
- Integrated Circuits and Semiconductor Failure Analysis
- Calibration and Measurement Techniques
- Nuclear Physics and Applications
- Copper Interconnects and Reliability
- Medical Imaging Techniques and Applications
- Astrophysical Phenomena and Observations
- Advanced X-ray and CT Imaging
- Astro and Planetary Science
- 3D IC and TSV technologies
- NMR spectroscopy and applications
- Advanced Data Storage Technologies
- Scientific Research and Discoveries
University of California, Davis
2015-2024
SLAC National Accelerator Laboratory
2024
New York University
2014-2015
Motorola (United States)
1992-2003
Fairchild Semiconductor (United States)
1987
Hewlett-Packard (United States)
1982-1983
California Institute of Technology
1976
With Australia Telescope Compact Array observations, we detect a highly elongated Mpc-scale diffuse radio source on the eastern periphery of Bullet cluster 1E 0657−55.8, which argue has positional, spectral and polarimetric characteristics relic. This powerful relic (2.3 ± 0.1 × 1025 W Hz−1) consists bright northern bulb faint linear tail. The emits 94 per cent observed flux highest surface brightness any known Exactly coincident with tail, find sharp X-ray edge in deep Chandra image –...
Abstract We describe the simulated sky survey underlying second data challenge (DC2) carried out in preparation for analysis of Vera C. Rubin Observatory Legacy Survey Space and Time (LSST) by LSST Dark Energy Science Collaboration (LSST DESC). Significant connections across multiple science domains will be a hallmark LSST; DC2 program represents unique modeling effort that stresses this interconnectivity way has not been attempted before. This encompasses full end-to-end approach: starting...
For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with standby leakage transistors and functional high-density SRAM cell size of 0.157 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Record NMOS/PMOS drive currents 1000/575 μA/μm, respectively, been achieved at 1 nA/μm off-current 1.1V V <inf xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> cost process. With this high...
We present deep 1.1-3.1 GHz Australia Telescope Compact Array observations of the radio halo bullet cluster, 1E 0657-55.8. In comparison to existing images this detection in our is at higher significance. The as extended X-ray emission direction cluster merger but significantly less than perpendicular direction. At low significance we detect a faint second peak close centroid smaller sub-cluster (the bullet) suggesting that, similarly emission, may consist two components. Finally, find that...
Context. The Mid-Infrared Instrument (MIRI) on board the James Webb Space Telescope (JWST) uses three Si:As impurity band conduction (IBC) detector arrays. output voltage level of each MIRI pixel is digitally recorded by sampling up ramp. For uniform or low-contrast illumination, ramps become nonlinear in a predictable way, but areas high contrast, nonlinearity curve becomes much more complex. origin effect poorly understood and currently not calibrated out data. Aims. We provide...
LSST Camera CCDs produced by the manufacturer e2v exhibit strong and novel residual charge images when exposed to bright sources. These manifest in following exposures both same pixel areas as source, pixels trailing between source serial register. Both of these pose systematic challenges Rubin Observatory Legacy Survey Space Time instrument signature removal. The latter trail region is especially impactful it affects a much larger area less well defined position. In our study this effect at...
In this work, we report on a detailed simulation of the Bullet Cluster (1E0657-56) merger, including magnetohydrodynamics, plasma cooling, and adaptive mesh refinement. We constrain with data from gravitational lensing reconstructions 0.5 - 2 keV Chandra X-ray flux map, then compare resulting model to higher energy fluxes, extracted temperature Sunyaev-Zel'dovich effect measurements, cluster halo radio emission. initial conditions by minimizing chi-squared figure merit between full 2D...
Hot carrier effects due to reverse biasing of emitter-base junction in a poly emitter bipolar transistor are discussed. Degradation current gain under DC, pulsed DC and AC stress conditions is found be determined by the total injected charge through biased junction. These results coupled with design simulations used predict reliability devices BiCMOS circuit.
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.124 . access stability write margin are significantly improved through a 50% Vt mismatch reduction, thanks HK-MG T <sub xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> scaling. Cell read current is increased 70% over Poly-SiON process. Ultra dense cell...
The Bullet Cluster (1E0657-56) merger is of exceptional interest for testing the standard cold-dark-matter plus cosmological constant model, and investigating possible existence a long- or short-range "fifth-force" in dark sector need modifications general relativity even Newtonian gravity. most recent previous simulations required an initial infall velocity far excess what would be expected within at least absence additional forces to We have carried out much more detailed simulations,...
This work presents a quantitative model which attributes most soft errors in dense SRAMs not to alpha particles as is commonly accepted, but cosmic ray events. also elucidates for the first time stored charge required SRAM cells achieve acceptable error rates. Enhancements add capacitance are necessary at 4 Megabit level and beyond. One method of enhancing cell reported detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Reduction of images and science analysis from ground-based telescopes such as the LSST requires detailed knowledge PSF image, which includes components attributable to instrument well atmosphere. Because atmospheric component is constantly changing, typically extracted each image by measuring size shape star across CCD, then building a fitting function over focal plane used model for extended sources galaxies. Since stars in CCD field have range brightnesses, accurate point varying...
A new scheme for a Side WAll Masked Isolation (SWAMI) process is presented which takes all the advantages provided by LOCOS without suffering its difficulties. The SWAMI technology incorporates sloped silicon sidewall and thin nitride layer around island sidewalls such that both intrinsic stress volume expansion-induced are greatly reduced. defect-free fully recessed zero bird's-beak local oxidation can be realized sloped-wall SWAMI. Fabrication NMOS electrical characteristics will...
An improvement in soft-error-rate (SER) achieved by implementing a triple-well structure BiCMOS process is discussed. For 4-Mb SRAMs fabricated process, an optimized improves the accelerated SER (ASER) over two orders of magnitude without compromising device performance. Diode charge collection and ASER measurements show excellent correlation across several CMOS processes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Context. The James Webb Space Telescope (JWST) has been collecting scientific data for over two years now. Medium Resolution Spectrometer (MRS) of the Mid-InfraRed Instrument (MIRI) one telescope’s most popular modes, and already produced ground-breaking results. Scientists are now looking deeper into new exciting discoveries, which introduces need to characterise correct known systematic effects reach photon noise limit. Five important limiting factors MRS pointing accuracy, non-linearity,...
We report a 100 nm modular bulk CMOS technology platform with multi Vt and gate oxide integrated transistors that enables device circuit co-design (M. Fukuma et al., VLSI Tech., 2000) techniques (e.g. well biasing power down/reduction) for low standby (LSP), high performance (HP), speed (HS), RF/analog system on chip (SoC) applications. The transistor performances are comparable to or better than recently reported data at the node. This also features an all-layer copper/low-k (<3.0)...
A dedicated simulator, Poisson_CCD, has been constructed which models astronomical CCDs by solving Poisson’s equation numerically and simulating charge transport within the CCD. The potentials free carrier densities CCD are self-consistently solved for, giving realistic results for distribution storage wells. simulator used to model that being construct LSST digital camera. output validated comparing its predictions with several different types of measurements, including astrometric shifts,...
Super steep retrograde channel profiles have been widely known to produce improved short characteristics in sub-0.35 /spl mu/m CMOS technologies. In this paper, an attempt is made leverage behaviour and thereby improve transistor performance (as measured by the current drive). Whereas significant improvements effects DIBL Delta/Vt/sub sat/ are obtained with channels, it observed that for a fixed gate length equal threshold voltage, transistors typically exhibit lower drive currents than...
We characterize the astrometric distortion at edges of thick, fully-depleted CCDs in lab using a bench-top simulation LSST observing. By illuminating an array forty thousand pinholes (30mu m diameter) object plane f/1.2 optical reimager, thousands PSFs can be imaged over 4Kx4K pixel CCD. Each high purity silicon pixel, 10mu square by 100mu deep, then individually characterized through series sub-pixel dithers X/Y plane. The unique character [response, position, shape] each as function flux,...
A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size less than 20 m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. WSi/sub x/ polycide emitter n-p-n transistor with an area 0.8*2.4 provides peak cutoff frequency (f/sub T/) 14 GHz collector-emitter breakdown voltage (BV/sub CFO/) 6.5 V. selectively ion-implanted collector (SIC) is compensate the base channeling tail in...
A new scheme for SWAMI (Side WAll Masked Isolation) process is presented which takes full advantage of LOCOS processing without suffering the difficulties. The technology incorporates a sloped silicon sidewall and thin nitride around island sidewalls such that both intrinsic stress volume expansion induced are greatly reduced. defect free near-zero bird's beak local oxidation can be realized by SWAMI. Fabrication MOSFET electrical characteristics will discussed. SWAMI/CMOS circuit including...
Future solid state imagers for high-spatial-resolution X-ray missions will require an unprecedented combination of small pixel size and large detector thickness. This presents challenges the accurate detection soft X-rays, since cloud charge produced by these photons near entrance window laterally diffuse to multiple pixels time it is collected rear surface electrodes, complicating photon energy reconstruction. Using realistic models electric field distribution in a silicon-based detector,...
This work discusses the trade-offs between 4T SRAM cells which use four bulk transistors (and have poly resistor or TFT loads) and 6T six PMOS loads). dominated stand-alone market since first introduced in 1970's, but been dominant for on-chip storage advanced microprocessors other logic circuits. However, recently there has a resurgence of interest stand alone applications. While are typically smaller, they generally require more complex process, poorer stability, especially at low voltage....
In this work components of the next generation 0.10 /spl mu/m CMOS technology are presented. They form core a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 Aring/ gate oxide (24 inversion Tox) while low power 25 (31 for reduced leakage. Gate lengths range from 65 nm high to 90 devices. Both 3.3 V 2.5 I/Os supported using 70 50 The backend employs low-k (k/spl sim/3) dielectric with multiple levels Cu metallization. density 6T SRAM...