A5045410186- Advancements in Semiconductor Devices and Circuit Design
- Silicon and Solar Cell Technologies
- Semiconductor materials and devices
- Chalcogenide Semiconductor Thin Films
- Semiconductor materials and interfaces
- Semiconductor Quantum Structures and Devices
- Quantum Dots Synthesis And Properties
- Thin-Film Transistor Technologies
- Radio Frequency Integrated Circuit Design
- solar cell performance optimization
- ECG Monitoring and Analysis
- Ferroelectric and Negative Capacitance Devices
- Analog and Mixed-Signal Circuit Design
- Silicon Carbide Semiconductor Technologies
- Nanowire Synthesis and Applications
- Conducting polymers and applications
- Perovskite Materials and Applications
- Graphene research and applications
- Innovation and Socioeconomic Development
- Photonic and Optical Devices
- Quantum and electron transport phenomena
- Neuroscience and Neural Engineering
- Photovoltaic System Optimization Techniques
- Silicon Nanostructures and Photoluminescence
- Organic Electronics and Photovoltaics
United International University
2014-2025
International Islamic University Chittagong
2011-2024
National Institute of Neurosciences & Hospital
2015
IBM (United States)
2008-2012
University of Florida
2006
Bangladesh University of Engineering and Technology
2000
For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with standby leakage transistors and functional high-density SRAM cell size of 0.157 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Record NMOS/PMOS drive currents 1000/575 μA/μm, respectively, been achieved at 1 nA/μm off-current 1.1V V <inf xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> cost process. With this high...
Band-gap engineering using SiGe channels to reduce the threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium (cSiGe) on silicon wafers for SOC applications unique challenges like oxidation rate differential with silicon, defectivity and interface state density unoptimized state, concerns...
In conventional models of base transit time in SiGe HBTs, the recombination is usually neglected because considered very thin to justify simplifications numerical calculation. Indeed, this assumption turns out not be valid at moderate injection levels, since carrier could have important consequences for transistor performance. The paper presents an analytical model, which includes process exponentially doped HBTs operating under intermediate conditions. inclusion makes mathematical solution...
As the world is progressing, futuristic innovation demand testing limits of design related to analog circuits. Thus with traditional MOSFET becoming more complex. In this paper, we propose use low-threshold voltage (LVT) instead MOSFET. Operational trans-conductance amplifiers were designed both and LVT MOSFETs a comparison was made. Further, fifth order low pass filter show it's effectiveness in removing noise from ECG signal. The simulation done Cadence, an industry -grade software, 45nm...
In this work, an analog front-end (AFE) circuit for electrocardiogram (ECG) detection system has been designed, implemented, and investigated in industry-standard Cadence simulation framework using advanced technology node of 45 nm. The AFE consists instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass second-order high-pass sections), notch filter—all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). OTAs have designed...
We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital RF/analog system-on-chip applications. To enable high-performance circuit design, we present challenging device features their enhancements. At nominal L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">poly</inf> , floating-body NFET PFET peak f xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> 300GHz fMAX higher than...
In this paper, a cylindrical double gate-all-around technology is merged with junctionless to maximize gate control as well avoid loss due the formation of junction in source-channel-drain region. This advancement allows downscaling all around FET (JL-CDGAA FET) up 5nm channel length acceptable performance many its parameters. A comparative study between JL-CDGAA and GAA also presented work.
In this work, a novel p-graphene/GrO IPCDTBT:PCBM/dye/AI based dye-sensitized solar cell (DSSC) has been designed, implemented, and investigated using Silvaco TCAD software. The proposed uses PCDTBT:PCBM as the solid electrolyte (ss-electrolyte) in place of commonly used P3HT to ensure higher efficiency. As front electrode, p-graphene is instead conventional ITO/FTO reduce cost. graphene oxide (GrO) hole transport layer (HTL) widely-used PEDOT:PSS enhance stability cell. Layer thicknesses...
In this work, an analog front-end (AFE) circuit for Electrocardiogram (ECG) detection system has been designed, implemented, and investigated in industry-standard Cadence simulation framework using advanced technology node of 45 nm. The AFE consists instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass second-order high-pass sections), notch filter- all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). OTAs have designed...
Conventional models for the Current-voltage characteristics of solar cells use numerical approach owing to inherent mathematical intractability. Although estimate almost accurate results, computational cost and time needed these is huge. These also lack physical insight. An analytical model is, therefore, necessary resolve issues. Based on concept perturbation theory, an has been proposed in this work deduce current-voltage CdS/CdTe thin-film having lightly doped absorber layer. The needs no...
This work proposes a Simulink-based Model of photovoltaic (PV) system using the two-diode model PV solar cell. The series and shunt resistance cell are estimated in this by an efficient iteration method. number required input parameters four based on available information from module datasheet. developed allows user to predict cell's current-voltage power-voltage characteristics curves varying sunlight, temperature, ideality factor value. is also applicable under partial shading/module...
This work proposes an analytical model incorporating the effects of series resistance to deduce current-voltage characteristics for ZnO/CZTS based thin film solar cell. The evolving mathematical intractability inclusion has been resolved by using concept perturbation theory. various utilizing proposed observed and analyzed. may be helpful gain more physical insight CZTS cells.
This paper focuses on developing an analytical model to analyze the current-voltage (J-V) characteristics of lightly doped CIGS-based thin film solar cell considering series resistance and voltage-space dependent electric field in absorber layer. The mathematical intractability evolved for these considerations has been resolved by employing concept perturbation theory. Effects various parameters such as intensity light, electron lifetime hole have investigated using developed model....
This work explores the opportunity of use graphene as transparent conducting (TC) layer instead conventional oxide (TCO) such indium tin (ITO) in CZTS based solar cells which is recently evolved one most promising thin film cells. It has been known that higher transmittance and conductance cheaper than widely used ITO. Based on MATLAB simulations, this proves can be better alternative ITO layer. Moreover, simulations show reduce amount material hence, cost cell optimum absorber width maximum...
In this letter, an aggressively scaled ion-sensitive field-effect tran- sistor (ISFET) has been proposed as a potential pH sensor with high sensitivity, low power consumption, and resolution. The associated transistor (FET) structure of the device is hetero-structured vertical tunnel FET Al <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$_{2}$</tex-math></inline-formula> O...
The analytical modeling of dark saturation current a solar cell conventionally incorporates either SRH (Schokley-Reed-Hall) recombination or Auger recombination, since simultaneous consideration both these mechanisms results in mathematical complexity. On the other hand, non-uniform doping profile is used practical cells for which retarding electric field introduced and as result, reduced. Moreover, level increases day by to meet requirements improvement performances. However, heavy well...
Buried oxide layer in SOI devices creates a few problems such as self-heating, which eventually flops the possibility of this device for future circuit analysis. A modification over fully depleted MOSFET merged with cylindrical gate all around (CGAA) structure is proposed work to incorporate improved performance along dissipate heat generated device. The buried replaced thin P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region and...
In this work, an analytical model has been developed for the dark saturation current in heavily-doped base region of a drift-field Si-solar cell. Unlike conventional models available literature, incorporates both SRH (Shockley-Read-Hall) and Auger recombination. The mathematical intractability due to consideration resolved by using elegant exponential approximation technique. simulations carried out shows that recombination becomes significant even 1 µm wide when surface velocity is lowered...
Based on the perturbation theory, an analytical model has been developed for J-V characteristics of lightly-doped CdTe-based thin film solar cells. The is computationally more efficient and provides better physical insight.
This paper attempts an analytical approach to accurately determine common-mode rejection ratio (CMRR) considering the effects of various non-idealities such as presence channel length modulation, body effect, finite resistance current source, mismatches in transconductances and drain resistances between two driver MOSFETS a common source CMOS differential amplifier. analysis brings light hitherto unforeseen dire impacts these put together on CMRR, hence strongly suggests that should not be,...