A5111740054- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Memory and Neural Computing
- Ferroelectric and Piezoelectric Materials
- Nanowire Synthesis and Applications
- Tissue Engineering and Regenerative Medicine
- Ferroelectric and Negative Capacitance Devices
- Copper Interconnects and Reliability
- Reconstructive Surgery and Microvascular Techniques
- Optical Coherence Tomography Applications
- Silicon Nanostructures and Photoluminescence
- Low-power high-performance VLSI design
- Electrospun Nanofibers in Biomedical Applications
- Ocular and Laser Science Research
- Advanced Sensor and Energy Harvesting Materials
- Advanced Optical Sensing Technologies
The University of Texas at Austin
1989-2024
Motorola (United States)
2002-2004
The authors have studied the feasibility of using ferroelectric materials as capacitor dielectric in one-transistor memory cells for 64-Mb and 256-Mb DRAMs. They performed an intensive literature search analysis. discuss crystal structure reviewed, their hysteresis curve, temperature dependence spontaneous polarization, leakage current, breakdown, reliability, ageing, fatigue. examine charge storage capacity a 1-T DRAM cell analyze number potential use capacitors, focusing on projected...
The memory cell and technology requirements issues for 64- 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected have been developed key parameters such as die size, area, capacity, capacitance leakage current, on-current. These an analysis assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 voltage difference, bit line capacitance. Pivotal specific to DRAM identified. It is...
The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. technology can be programmed erased techniques in floating gate memories substantially reduce the cost of embedded flash at node beyond.
In this work components of the next generation 0.10 /spl mu/m CMOS technology are presented. They form core a platform encompassing logic, non volatile memory, and analog blocks. High performance bulk devices use 18 Aring/ gate oxide (24 inversion Tox) while low power 25 (31 for reduced leakage. Gate lengths range from 65 nm high to 90 devices. Both 3.3 V 2.5 I/Os supported using 70 50 The backend employs low-k (k/spl sim/3) dielectric with multiple levels Cu metallization. density 6T SRAM...
Multi-Exposure Speckle Imaging (MESI) utilizes laser speckle for visualizing flow and quantifying changes. Using a coherent source to illuminate the sample, reflected pattern is captured at various exposure times, enabling estimation of dynamics. Free space MESI setups have fixed imaging geometry limiting flexibility in certain applications such as handheld, bandage integrated, or endoscopic systems. This study explores use an optical fiber bundle capture pattern. A containing 18,000...
Free flap surgeries are critical for repairing extensive tissue damage caused by tumor resections, congenital deformities, or traumatic injuries. These procedures involve transferring vascularized from a donor site to recipient promote wound healing. The success of free depends on adequate perfusion the flap. Postoperative monitoring is essential, as complications such vascular occlusion can lead hypoxia and failure, necessitating additional surgeries. This review focuses reconstruction...
This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The NOR Flash can be programmed erased techniques in floating gate memories. Key aspects of this technology are ability to form nanocrystals right size density, protect them from subsequent processing effects remove undesired areas. use isolated for charge storage provides opportunity reduce program erase voltages due tunnel...