A5001428686- Advancements in Photolithography Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Electron and X-Ray Spectroscopy Techniques
- Advanced Surface Polishing Techniques
- Semiconductor materials and devices
- Nanofabrication and Lithography Techniques
- 3D IC and TSV technologies
- Optical Coatings and Gratings
- Advanced optical system design
- Industrial Vision Systems and Defect Detection
- Advancements in Semiconductor Devices and Circuit Design
- Copper Interconnects and Reliability
- Image Processing Techniques and Applications
- Silicon and Solar Cell Technologies
- Advanced Measurement and Metrology Techniques
- Plasma Diagnostics and Applications
- Semiconductor Lasers and Optical Devices
- Welding Techniques and Residual Stresses
- Optical measurement and interference techniques
- Surface Roughness and Optical Measurements
- Advanced X-ray Imaging Techniques
- Low-power high-performance VLSI design
- Surface and Thin Film Phenomena
- Non-Destructive Testing Techniques
- Ferroelectric and Negative Capacitance Devices
IMEC
2015-2024
Imec the Netherlands
1994-2010
KU Leuven
1994-2010
With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews latest trends advances enable scaling. Dimensional scaling, enabled by EUV lithography, will continue with multi-patterning. Higher costs multi-patterning be mitigated high (0.55) numerical aperture (NA) simplifying patterning potentially leading higher yield. Logic standard cell scaling below 6-track (6T) adequate...
EUV lithography is currently the state-of-the-art technology that used for printing most critical layers in advanced logic and DRAM chips. It uses a 13.5-nm wavelength, projection optics have numerical aperture (NA) of 0.33. has taken over from 193-nm immersion where more multiple patterning steps were needed to print these layers, resulting higher cost, longer turnaround time (TAT), reduced yield. The newest developments are further push resolution by building NA lens. For that, ASML Zeiss...
ASML has built and shipped to The College of Nanoscale Science Engineering the University at Albany (CNSE) IMEC two full field step-and-scan exposure tools for extreme ultraviolet lithography. These tools, known as Alpha Demo Tools (ADT), will be used process development set foundation commercialization this technology. In paper we present results from set-up integration both ADT systems, status resist reticles EUV, plans using these research centers. We also first images one customer site,...
Moore's Law (Moore's Observation) has been driving the progress in semiconductor technology for past 50 years. The industry is at a juncture where significant increase manufacturing cost foreseen to sustain trend of dimensional scaling. At N10 and N7 nodes, struggling find cost-friendly solution. device level, technologists have come up with novel devices (finFET, Gate-All-Around), material innovations (SiGe, Ge) boost performance reduce power consumption. On other hand, from patterning...
At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, can actively help exploring options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme be optimized achieve a dense SRAM cell; optimizing device performance lead smaller standard cells; metal interconnect stack needs adjusted unidirectional metals vertical transistor shift design paradigms. This...
Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter wavelengths or higher numerical apertures have allowed lithography be on forefront dimensional for industry. Unfortunately, roadmap is currently at a juncture major paradigm shift. EUV Lithography steadily maturing but not fully ready inserted into HVM. there are no alternative litho candidates horizon that can take over from 193nm. As result, it...
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a became challenging and expensive push beyond for complex features that can be tackled in simpler manner Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part high-volume manufacturing device landscape it reached critical decision point where one further single print on 0.33NA full field scanner or move EUV double...
BackgroundTo print ever smaller features at high contrast projection lithography technology has evolved to shorter wavelength light and larger numerical aperture (NA). After enabling the extreme-ultraviolet (EUV) wavelength, industry is looking into increasing NA. At NA's much higher than 0.55, new effects such as polarization will start play a role, impact of ultimate mask resolution material interactions expected. Already NA small loss predicted due use unpolarized in scanner. Further...
This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes couple of solutions. For N10 design, we opted line staggering approach which each line-end ends contact. We highlight challenges to obtain reasonable window, both simulation as exposures wafer. The main come from very complex keep mask, consisting complicated 2D structures are challenging 193i litho. Therefore, propose solution perform traditional LELE top mandrel...
The extreme ultraviolet lithography (EUVL) program at IMEC is aimed to tackle many unsolved critical issues of EUV as the technology moves towards production, by focusing specifically on tool, resist, and mask projects. Here, authors describe structure EUVL status alpha demo tool. In particular, they discuss their proposed strategies for flare mitigation shadowing effect correction. They demonstrate how it possible implement an effective rule-based strategy. addition, propose a relatively...
IMEC has started an EUV lithography research program based on ASMLs full field scanner, the Alpha Demo Tool (ADT). Currently, ADT is in final phase of installation. The focuses three main projects: resists, reticles and assessment performance. intent this to help improve establish necessary mask resist infrastructure. In paper, status progress reviewed. preparation for a process ADT, interference been used track Steady development seen, especially terms resolution, as some materials are now...
Three major technological lithography options have been reviewed for high volume manufacturing at the 32 nm half pitch node: 193 immersion with index materials, enabling NA > 1.6; double patterning and EUV lithography. In this paper evolution of these three over 2008 is discussed. The extendibility beyond important final choices to be made. During 2008, work on has stopped due lack progress in optical material liquid development. Double made a lot but cost concerns still exist. Preferred are...
Extreme Ultra-Violet lithography (EUVL) is considered as the most promising candidate to replace optical from 14nm technology node onwards. EUVL has recently been supplanted by multiple patterning using existing 193nm immersion tools for upcoming 14 nm due current resolution limitations and production level efficiency restrictions. In this paper, a wafer cost model 28nm down developed. It identifies module key component where innovation can be leveraged reduce cost. The results presented in...
EUV lithography is generally considered as the technology to take over from 193nm immersion lithography, but has been delayed due a number of critical problems that remain be solved. The purpose this paper illustrate improvements in process complexity, reduced design restrictions and processing costs case EUVL would available for 14nm logic node beyond. We have shown readiness keep scaling devices following pace Moore's law, continuing performance at an acceptable cost cycle time, still...
It is shown by simulation that the line edge roughness (LER) on gates causes fluctuations transistor performance [J. A. Croon et al., “Line roughness: Characterization, modeling, and impact device behavior,” Proceedings of IEDM, 2002; “Experimental investigation line-edge MOSFET yield” (to be published)]. Efforts are underway to investigate influence experimentally. In this article, transfer LER resist pattern into poly silicon layer investigated. For experimental setup isolated gate lines...
EUV lithography is one of the hot candidates for 22nm node. A well known phenomenon in impact non-telecentricity and mask topography on printing performance. Due to oblique illumination mask, layout, printed features are shifted biased wafer with respect their target dimension up several nanometers. This effect inherent imaging systems. In order maintain CDU, overlay registration requirements, these effects need be compensated as part lithographic manufacturing process. Conventional...
A combination of blank inspection (BI), patterned mask (PMI) and wafer (WI) is used to find as many possible printing defects on two different EUV reticles. These multiple inspections result in a total population known each reticle. The printability these first confirmed by review wafers exposed the full field ASML Alpha Demo Tool (ADT) at IMEC. Subsequently reticle performed corresponding locations with both SEM (Secondary Electron Microscope) AFM (Atomic Force Microscope). This methodology...
In this follow-up paper for our contribution at BACUS 2010, first evidence is shown that also the more advanced Lasertec M7360 has missed a few printing reticle defects caused by an imperfection of its EUV mirror, so-called multilayer defect (ML-defect). This work continued to use combination blank inspection (BI), patterned mask (PMI) and wafer (WI) find as many possible on reticles. The application inspection, combined with separate repeater analysis each multiple focus conditions used...
The EUV program at imec aims identifying the critical issues to prepare lithography for insertion into high volume IC production. started in 2006 with 0.25 NA ASML Alpha Demo Tool and has since then evolved around several focus areas. 1) scanner performance, reliability monitoring, 2) definition verification of OPC strategies generic specific imaging effects 3) reticle defectivity, focusing on multi-layer defects, handling cleaning, 4) resist screening, identification materials that not only...