A5069736243- Semiconductor materials and devices
- Copper Interconnects and Reliability
- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Surface Polishing Techniques
- Semiconductor materials and interfaces
- Advancements in Photolithography Techniques
- Metal and Thin Film Mechanics
- Electrodeposition and Electroless Coatings
- Advanced ceramic materials synthesis
- Ferroelectric and Negative Capacitance Devices
- Advanced Memory and Neural Computing
- Anodic Oxide Films and Nanostructures
- Nanofabrication and Lithography Techniques
- Low-power high-performance VLSI design
- VLSI and Analog Circuit Testing
- Electron and X-Ray Spectroscopy Techniques
- Electromagnetic Compatibility and Noise Suppression
- Advanced machining processes and optimization
- Electrical Contact Performance and Analysis
- Radio Frequency Integrated Circuit Design
- Synthesis and properties of polymers
- Magnetic properties of thin films
IMEC
2015-2024
KU Leuven
1999-2015
Imec the Netherlands
2012
Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in wide single damascene lines using an ALD process combination with 2.5 Å TiN interface and postdeposition annealing. At such small dimensions, effective resistance depends less on scaling than that Cu/barrier systems. Ruthenium potentially crosses Cu curve at 14 10 according to semiempirical model advanced These...
This paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu Cu pads of unequal size and surface topography for the top bottom wafers. The use SiCN dielectrics allows obtain high W2W energy (> 2 J/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at low annealing temperature (250 °C). Excellent is obtained after 350 °C. A CMP process, resulting...
This paper presents our approach to hybrid bond scaling 1μm pitch and recent demonstration results. The direct wafer stacking of two Cu/SiCN surface is realized between slightly protruding Cu nano-pad on one recessed, but larger, the second wafer. tailored as smaller than recessed compensate for overlay tolerance in wafer-to-wafer (W2W) bonding. To control stability performance integration process, intensive inline atomic force microscopy (AFM) acoustic (SAM) characterization used various...
In this paper, we optimize the stack of a 90-nm CMOS-friendly <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm W}\backslash{\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$</tex></formula> conductive-bridging random access memory cell integrated in one-transistor/one-resistor configuration. We show that excellent Cu buffering properties TiW layer inserted at interface make it possible, on one hand, to...
We investigated plasma treatment induced water absorption in a SiOCH low-k dielectric and the influence of absorbed components on reliability. By using thermal desorption spectroscopy (TDS), was evidenced for N2/H2 treatments. Based these TDS results, two anneal temperatures were selected to separate quantify respective contributions components, physisorbed (α) chemisorbed (β) water, With desorbed by an at 190 °C, shows reduced leakage currents slightly improved time-dependent breakdown...
We demonstrate 10 nm half-pitch (HP) Ruthenium interconnects filled by atomic layer deposition (ALD). The resistivity and the cross-sectional area of were determined via Matthiessen's rule method. find that Ru was rather independent interconnect, increasing from 12 µΩcm for larger lines to 15–17 areas 200–300 nm2. HP showed no electromigration failures at 5 MA/cm2 300°C during 1000 hours. Time-dependent dielectric breakdown measurements indicated does not require a diffusion barrier on both...
High performance 3D integration Systems need a higher interconnect density between the die than traditional μbump interconnects can offer. For ultra-fine pitches below 5μm different solution is required. This paper describes hybrid wafer-to-wafer (W2W) bonding approach that uses Cu damascene patterned surface bonding, allowing to scale down interconnection pitch 5 μm, potentially even 1μm, depending on achievable W2W accuracy. The method referred as since of Cu/dielectric surfaces leads...
The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to CMOS flow with industrially available tools is high interest for the electronics industry because such can produce more compact systems. We present 300mm industry-compliant via-middle TSV module, an advanced high-k/metal gate platform. TSVs are fabricated by Bosch after contact and before first metal layer. target copper diameter 5μm via depth in silicon substrate 50μm. Dense structures have...
High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu rails. The HAR feature boost performance by reducing resistance and voltage drop along the line. nature, helps to minimize standard cell height freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, lines of aspect ratio 7, a CD 18 nm. Line these dimensions, measures 60 Ω/µm, with minimum electrical...
Excellent tunnel magneto resistance (TMR) values of 143% at resistance-area products (RA) 4.7 Ωμm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from 11nm thin Co/Ni based perpendicular magnetic junctions (p-MTJ) was achieved. Engineered wetting layer (WL), seed (SL) and the introduction newly designed inner synthetic anti-ferromagnetic (iSAF) pinned in combination with ultra-smooth bottom electrode (roughness 0.5 Å) yielded to...
Knowledge of the geometry effect on impurity incorporation and grain growth in narrow lines is important for reducing copper line resistivity. In this paper, we investigate with time-of-flight secondary ion mass spectroscopy. We also study influence linewidth, trench depth, pattern density, overburden reduced dimensions. The concentration chlorine carbon found to increase decreasing while sulfur close detection limit. This contributes superfilling consistent curvature-enhanced accelerator...
In this paper we demonstrate excellent memory performances of a 90nm CMOS-friendly W\Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> \TiW\Cu CBRAM cell integrated in 1T1R configuration and withstanding the back-end line thermal budget 400°C. The exhibits low-power highly controlled set reset operations, allowing reversible multilevel programming by both current voltage. Low-voltage...
Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative scheme studied based on the replacement of a sacrificial template ultralow-k dielectric. A metal structure first formed patterning material. After removal, k = 2.31 spin-on type porous low-k dielectric deposited onto patterned lines. The chemical and electrical properties dielectrics are blanket wafers, indicating that during hard bake, most porogen...
3D stacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at 45nm fin pitch and 110nm poly technology. This demonstrates the compatibility of aggressive device density advanced nodes thanks to tight alignment precision first processed top layer last bottom through silicon channel bonding stack during 193nm immersion lithography. The are junction-less fabricated low temperature (T ≤ 525 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.
Self-forming barriers and advanced liner materials are studied extensively for their Cu gapfill performance interconnect scaling. In this paper, 22nm 1/2 pitch low-k interconnects with barrier (Mn-based, TaN) /liner (Co, Ru) combinations compared benchmarked resistivity, resistance scaling, electromigration (EM) performance. Extendibility to 16nm copper width was explored experimentally a projection towards 12nm is performed. It found that the Ru-liner based systems show higher overall...
Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well potential new conductor materials.
For many years traditional 193i lithography has been extended to the next technology node by means of multi-patterning techniques. However recently such a became challenging and expensive push beyond for complex features that can be tackled in simpler manner Extreme UltraViolet Lithography (EUVL) technology. Nowadays, EUVL is part high-volume manufacturing device landscape it reached critical decision point where one further single print on 0.33NA full field scanner or move EUV double...
Higher performance, higher operation speed and volume shrinkage require high 3D interconnect densities. A way to meet the density specifications is further increase A.R. of TSV interconnection. This requires integration highly conformal thin films deposition techniques in flows, particularly for metallization. In this study, seed layer enhancement applied regular PVD Cu metalizing diameter 2μm aspect-ratio 15:1. The results reported paper open a new path process TSVs provide versatile...
This work reports metal exploration for buried power rail (BPR) and Via-to-BPR (VBPR) towards the 1 nm node. For tungsten, which is first choice of BPR at 3 node, we optimize W metallization stack to minimize line resistivity, together with ways reduce W-BPR - W-VBPR contact resistance (R). scaled CDs 2 nodes, introduce molybdenum level benchmark its R electromigration against Ru metallization. Additionally, Mo dry & wet, selective etch processes enable Mo-BPR recess in fin/STI fin pitch 24...
3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, junction-less are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and Si:P SiGe:B 60% raised SD for NMOS PMOS respectively. Device matching, analog RF performance tier in-line state-of-the-art Si technology (>1000°C). layer is transferred on CMOS planar bulk wafers W metal-1 interconnects, using...
NiAl lias been investigated as a potential alternative for Cu in future interconnect metallization schemes. Backthinning experiments of thick films (> 50 nm) by IBE or CMP leads to large grain sizes small thicknesses. deposited at 420°C PVD shows resistivity 17 μΩcm 10 nm film. Combining deposition epitaxial on Ge (100) with backthinning using led lower than Ru: 11.5 7.7 and 10.6μΩcm 17.2 nm.
This work reports on aggressively scaled replacement metal gate, high- k last devices (RMG-HKL), exploring several options for effective function (EWF) engineering, and targeting logic high-performance low-power applications. Tight low-threshold voltage ( V T ) distributions NMOS are obtained by controlled TiN/TiAl-alloying, either using RF-physical vapor deposition (RF-PVD) or atomic layer (ALD) TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at bottom gate...
An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, thermal WN barrier, an electroless NiB platable seed and throughput copper ECD filling process. Because of the conformality barrier seed, these layers can be deposited very thinly, reducing cost significantly, while still guaranteeing continuous barrier/seed all along sidewall till bottom TSV. This has been successfully processed on 3 m diameter 50 deep TSVs, showing void-free fill in...
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, junctionless (JL) devices are fabricated with maximum processing temperature of 525 °C. The feature high k/metal replacement gate and low-temperature Si:P SiGe:B 60% raised source drain for nMOS pMOS fabrication, respectively. Device matching, analog, RF performance tier in-line state-of-the-art Si technology (>1000 °C). JL operate reduced electric field...