A5031748112- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Copper Interconnects and Reliability
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and interfaces
- Phase-change materials and chalcogenides
- Metal and Thin Film Mechanics
- Electronic and Structural Properties of Oxides
- 3D IC and TSV technologies
- Transition Metal Oxide Nanomaterials
- Anodic Oxide Films and Nanostructures
- Electronic Packaging and Soldering Technologies
- Metallurgical and Alloy Processes
- Advanced Materials Characterization Techniques
- Thin-Film Transistor Technologies
- Advancements in Photolithography Techniques
- Additive Manufacturing and 3D Printing Technologies
- Ferroelectric and Piezoelectric Materials
- Chalcogenide Semiconductor Thin Films
- Photonic and Optical Devices
- Electrocatalysts for Energy Conversion
- Ion-surface interactions and analysis
- Electron and X-Ray Spectroscopy Techniques
IMEC
2013-2024
Universidade de São Paulo
2018
KU Leuven
2008-2015
Imec the Netherlands
2004-2008
Ternary oxides, GdScO3, DyScO3, and LaScO3, deposited by pulsed laser deposition using ceramics targets of stoichiometric composition, were studied as alternative high-k gate dielectrics on (100) Si. Their physical characterization was done Rutherford backscattering, spectroscopic ellipsometry, x-ray diffraction, transmission electron microscopy blanket layers Si, electrical capacitors. It is found that DyScO3 GdScO3 preserve their amorphous phases up to 1000°C. Other encouraging properties...
For 28-nm embedded application, we have proposed a TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies structures: low-damage etching, side oxidation encapsulated structure. As result, succeeded for the first time in forming at center. In addition, confirmed feasibility of 20-nm size....
Density functional theory simulations are used to identify the structural factors that define material properties of ovonic threshold switches (OTS). They show nature mobility‐gap trap states in amorphous Ge‐rich Ge 50 Se is related GeGe bonds, whereas Se‐rich 30 70 valence‐alternating‐pairs and lone‐pairs dominate. To obtain a faithful description electronic structure delocalization states, it required combine hybrid exchange–correlation functionals with large unit‐cell models. The extent...
We report on novel integrated Se-based Ovonic Threshold Switching selector devices, with sizes down to 50nm, which can be operated reliably at high drive current densities, exceeding 20MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and have half-bias nonlinearity well 10 xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . show functional devices after a thermal budget of 350°C. Their electrical properties are tunable by careful...
The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to CMOS flow with industrially available tools is high interest for the electronics industry because such can produce more compact systems. We present 300mm industry-compliant via-middle TSV module, an advanced high-k/metal gate platform. TSVs are fabricated by Bosch after contact and before first metal layer. target copper diameter 5μm via depth in silicon substrate 50μm. Dense structures have...
An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with drive current exceeding 1MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and half-bias nonlinearity of 1500. Excellent reliability fully demonstrated on 40nm-size crossbar structures, statistical ability to withstand bipolar cycling over 10...
We engineer a scalable and CMOS-friendly RRAM stack using down to 3nm ALD-based Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> . The 20nm-sized TiN\Ta \Ta device operated at 50μA exhibits ultra-fast write (~5ns) moderate voltage (<;2V) with >10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> endurance. also demonstrate excellent disturb retention characteristics, which we...
We report on the reduction of leakage current at half threshold bias (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off1/2</sub> ) down to 1nA range achieved using Se-enriched or N-doped GeSe. Integrated 50nm OTS devices demonstrated excellent thermal stability up 600°C, as well electrical (V xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> , I when operated a high density 23MA/cm <sup xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...
We demonstrate suppression of the overshoot current effect on a resistive random access memory device with TiN/Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> /TaO xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /TaN/TiN stack structure. Using test structures an integrated 5-kΩ series resistor, nearly 1:1 relation between compliance and first maximum reset has been achieved,...
For 28-nm embedded application, we have proposed a TaO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -based ReRAM with precise filament positioning and high thermal stability. The cell was realized using several newly-developed process technologies structures: low-damage etching, side oxidation encapsulated structure. As result, succeeded for the first time in forming at center. In addition, confirmed feasibility of 20-nm size....
Ru thin films were deposited by plasma enhanced atomic layer deposition using MethylCyclopentadienylPyrrolylRuthenium (MeCpPy)Ru and N2/NH3 plasma. The growth characteristics have been studied on titanium nitride or tantalum substrates of various thicknesses. On SiO2, a large incubation period has observed, which can be resolved the use metal ∼ 0.8 nm. layers ultra-thin are similar to those thick despite fact that not fully closed. Scaled Ru/metal stacks in narrow lines down 25 nm width....
This study is focused on Conductive Bridging Random Access Memory (CBRAM) devices based chalcogenide electrolyte and Cu-supply materials, aims at identifying the key material parameters controlling memory properties. The CBRAM investigated are integrated CMOS select transistors, constituted by either Ge-Se or Ge-Te layers of various compositions combined with a Cu2GeTe3 active electrode. By means extensive physical electrical characterization, we show for given system that slower write...
We investigate the electronic structure and defects of Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> Se xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> materials at atomic level, using full-layer-thickness (5nm) amorphous models. In Ge-rich , nature mobility gap is mostly related to miscoordinated Ge. The population/localization mobility-gap states changes solely under effect electric field. Strong covalent bonds introduced by...
This work reports on aggressively scaled replacement metal gate, high- k last devices (RMG-HKL), exploring several options for effective function (EWF) engineering, and targeting logic high-performance low-power applications. Tight low-threshold voltage ( V T ) distributions NMOS are obtained by controlled TiN/TiAl-alloying, either using RF-physical vapor deposition (RF-PVD) or atomic layer (ALD) TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at bottom gate...
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions minimum island, via extension and tip-to-tip (T2T). Five-track place route (PNR) SRAM constructions were realized with self-aligned block (SAB) technique. Stacked vias showed resistance modulation size island due change in chamfer. High...
In this abstract, we report for the first time low-current performance enhancement combined with improvement of scaling potential in CBRAM devices by adopting an etch-friendly alternative material, Co, as active electrode, based on theoretical considerations and experimental results. Co is proven to yield, respect Cu, faster/lower voltage switching more stable conductive filaments, irrespective layer, thanks its higher cohesive energy. By further optimizing show that introduction electrode a...
Rare-earth scandate materials have been identified as candidates for gate dielectrics in metal oxide semiconductor transistors because of their high thermal stability against crystallization combination with a high-dielectric constant. In this study, tris(1-methoxy-2-methyl-2-propoxy)dysprosium [] and are evaluated metallorganic chemical vapor deposition precursors on silicon at moderate temperatures . These allow easy integration into standard transistor flow. The layers uniform close to...
Material screening of gate dielectrics for complementary metal oxide semiconductor applications is often complicated by the inability to deposit test samples. We examine aqueous chemical solution deposition (CSD) technique as a simple, inexpensive, and fast thin metal-oxide layers. deposited layers on . The thinnest stack yielded an equivalent thickness (EOT) with gate-leakage current at EOT scales linearly physical thickness, allowing -value extraction, approximately 14. Our results suggest...
A gate-first process was used to fabricate CMOS circuits with high performing high-K and metal gate transistors. Symmetric low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> values of plusmn 0.25 unstrained I xmlns:xlink="http://www.w3.org/1999/xlink">DSAT</sub> 1035/500 muA/mum for nMOS/pMOS at xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> =100nA/mum |V xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> |=1.1 are demonstrated...
In this work, we studied molybdenum (Mo) and its conductive oxides for p-type metal gate application. Three compositions of have been investigated. The resistivity was found to significantly increase with the oxygen incorporation. A clear phase separation all observed after high-temperature thermal treatment. incorporation be effective work function (WF) Mo. However, full device integration, a significant WF decrease observed, which may induced during junction activation process. This...