Christophe Lorant
A5062072211- Semiconductor materials and devices
- 3D IC and TSV technologies
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Copper Interconnects and Reliability
- Advancements in Photolithography Techniques
- Semiconductor materials and interfaces
- Electronic Packaging and Soldering Technologies
- Thin-Film Transistor Technologies
- Optical Coatings and Gratings
- Nanofabrication and Lithography Techniques
- Industrial Vision Systems and Defect Detection
- Advanced Memory and Neural Computing
- Plasma Diagnostics and Applications
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Silicon Carbide Semiconductor Technologies
IMEC
2016-2023
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. technology requires insertion metal in front-end-of-line (FEOL) stack. poses risks stack deformation and device degradation due to metal-induced stress contamination. To assess deformation, we demonstrate W-BPR which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting...
The main limitations of the current dynamic random access memory (DRAM) technology are its scalability and power consumption. These constraints can be overcome by using an In–Ga–Zn–oxide (IGZO) transistor that offers a low OFF-current high scalability. For that, IGZO device performance needs to optimized, which includes increasing <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{...
We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, tight variability and matching control. On the wafer's frontside (FS), M1 lines (FSM1) through V0 vias to M0A which then linked BPR by called VBPR while also contacting directly device's S/D-epi. As for gate wiring, enable in this work its access is landing it neighboring line set only field-oxide. A single-step metallization preceded situ...
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions minimum island, via extension and tip-to-tip (T2T). Five-track place route (PNR) SRAM constructions were realized with self-aligned block (SAB) technique. Stacked vias showed resistance modulation size island due change in chamfer. High...
Fan-Out wafer level packaging has seen rapid adoption over the last few years due to its form factor, performance, and cost advantages compared 3D techniques. Redistribution layers (RDL) are used route very high density connections on chip much lower of substrate. Multiple RDL required in order match line chip. This turn increases total package. Decreasing metal width for supports reducing number redistribution levels decreasing cost. Reducing requires tightening requirements lithography...
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, first time, integration of tungsten (W) BPR lines with Si finFETs. The characteristics in close proximity to floating are found be similar without BPR. Moreover, W-BPR interface Ru via contact can withstand more than 320 h electromigration (EM) stress at 4 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 330°C,...
This paper reports BPR/Via-to-BPR (VBPR) module development at 24nm fin pitch (FP) / 42nm contacted gate (CPP), and W Ru-BPR Ru- Contact-to-Active (M0A)/VBPR resistance (R) & electromigration (EM). BPR dielectric barrier, plug reveal are optimized to enable scaling. A self-aligned VBPR etch is also demonstrated by Q-ALE process. meets line R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">target</sub> <; 50 Ω/μm ~2× smaller aspect ratio than...
For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with 0.0205 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, design layout is shown, key steps are explained in detail. NMOS functional device characteristics analyzed.
This work reports on some key integration aspects for 3D devices fabrication, focusing first the impact of thermal and plasma treatments at gate module triple-gate finFETs their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more wires vertically stacked) vertical configuration. The selected doping schemes metals also powerful knobs to engineer interface properties. In addition, specific steps NWFETs, such as release...
Metal oxide or metal nitride films are used as hard mask materials in the semiconductor lithography processes due to their excellent etch resistances against plasma etches. Chemical vapor deposition (CVD) atomic layer (ALD) techniques usually deposit containing on substrates underlying films, which uses specialized equipment and can lead high cost-of-ownership low throughput. The present paper describes formation functional properties of novel masks by simple solution spin coating process....
While the semiconductor industry has reached high-volume manufacturing of 7 nm technology node (N7), patterning processes for future nodes N5, N3 and even below, are being investigated developed by research centers. To achieve critical dimensions gratings these nodes, we require multipatterning approaches, such as self-aligned double/quadruple/octuple (SADP/SAQP/SAOP) multiple litho-etch (LE) patterning, in combination with 193i lithography EUV lithography. These need to be subsequently cut...
We report on scaled finFETs with a novel routing scheme enabling connection via buried power rails (BPR) from both wafer sides, tight variability/matching control. On the frontside (FS), contacting to p/n S/D-epi and BPR is done, after M0A VBPR vias patterning, in single metallization step an optimized preclean reducing R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ext</inf> while preserving good BPR-VBPR contact interface. After flipping,...
Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling dynamic random access memory (DRAM) technology. In this paper, the CMOS integration diffusion and replacement (D&GR) investigated, evaluating four different approaches for critical patterning step removing N-type field effect transistor (NFET) effective work function (eWF) shifter stack from P-type (PFET) area. The plasma exposure during investigated detail found have strong...
A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch 0.0205 um2 are presented, emphasis on process challenges innovations. new DTCO/TCAD methodology is used to explore the design space, demonstrate bit cell functionality optimize process. In particular, it shown that vertical SGT extremely sensitive misalignment buried bottom contact makes immune doping variations misalignments.
As conventional pitch scaling is saturating, boosters such as buried power rail (BPR) [1-4] and its extension to backside delivery (BSPDN) [5, 6] could provide 20% 30% area gain [7], respectively. BPR can also help improve SRAM design [8] a building block in novel architectures CFET [9, 10], for technology beyond the 3 nm CMOS node. The two main features of include: (i) introduction metal within fin module (fig. 1). Metal insertion front-end-ofline (FEOL) has risk tool/wafer...
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 pitch layer, is demonstrated. Place-and-route (PnR) simulations the Power Delivery Network (PDN) proved IR-drop reduction with respect to stacked-via configuration. SV first and last approaches were electrically tested using full barrierless ruthenium (Ru) on dielectric low-k 3.0. A maximum AR = 3.8 was achieved ~2.4 times lower resistance than alternative Thermal shock tests...
The surrounding-gate-transistor (SGT) is a vertical gate-all-around device with new design to exploit natural area gain for further scaling the SRAM size beyond N5 node. One of benefits in SGT it can fully decouple dependency gate length (Lg) and source/drain (S/D) contact from pitch (CGP) scaling, which seen as hard limit conventional scaling. To realize benefit Lg independent lithography, patterning challenges 3D structure must be resolved. In this paper, we report MOL fabrication, such...
There is a growing interest in new spin on metal oxide hard mask materials for advanced patterning solutions both BEOL and FEOL processing. Understanding how these respond to plasma conditions may create competitive advantage. In this study development was done two challenging applications where the traditional Si based films were replaced by EMD oxides, which acted as highly selective masks. The biggest advantage of masks lays process window improvement at lower or similar cost compared...
Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks ever increasing device performance density, reduced cost power consumption. To keep industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at 22nm technology node [1]. These devices continue be subject of many innovations but face challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing...
The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven to 10nm technology node beyond ushered a new era of high-performance 3-dimensional transistor structures. Consequently, surface preparation is becoming more challenging especially particulate contamination will continue be concern at increasingly demanding levels. Maly equation, with its use Poisson distribution, continues used predict allowable defect density front particles...