A5035980017- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Silicon and Solar Cell Technologies
- Semiconductor materials and interfaces
- Integrated Circuits and Semiconductor Failure Analysis
- Nanowire Synthesis and Applications
- Thin-Film Transistor Technologies
- Semiconductor Quantum Structures and Devices
- 3D IC and TSV technologies
- Photonic and Optical Devices
- Silicon Carbide Semiconductor Technologies
- Advanced Surface Polishing Techniques
- Advancements in Photolithography Techniques
- Silicon Nanostructures and Photoluminescence
- Ferroelectric and Negative Capacitance Devices
- Diamond and Carbon-based Materials Research
- Electron and X-Ray Spectroscopy Techniques
- Ion-surface interactions and analysis
- Advanced Materials Characterization Techniques
- Advanced Data Storage Technologies
- Metal and Thin Film Mechanics
- Quantum Dots Synthesis And Properties
- Semiconductor Lasers and Optical Devices
- Chalcogenide Semiconductor Thin Films
- Quantum and electron transport phenomena
Soitec (France)
2024-2025
IMEC
2015-2024
KU Leuven
2007-2021
GlobalFoundries (United States)
2015
Imec the Netherlands
2007-2014
Ghent University
2002-2007
We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). show that these devices, which were fabricated bulk substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL 42 mV/V for L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> 24 nm) at performance levels comparable to finFET reference...
This paper presents a new integration scheme to fabricate Si/Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.55</sub> Ge xmlns:xlink="http://www.w3.org/1999/xlink">0.45</sub> heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. 1- μm length on excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed suppress trap-assisted (TAT), reveal the point...
We report on the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs, with matched threshold voltages (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t, sat</sub> ~ 0.35 V) for N- and P-type devices. The Vt setting is enabled by nanowire-compatible dual-work-function metal in a high-k last replacement gate process. Furthermore, we demonstrate that junction formation can influence release differently due to...
We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A CFET process is cost effective compared to a sequential process. The small N/P separation in results lower parasitics and higher performance gains. In this paper, fabrication flow, we demonstrate functional PMOS FinFET bottom devices NMOS nanosheet FET top devices. Process development all critical modules enable these are presented. Monolithic scheme...
We investigate scalability, performance and variability of high aspect ratio trigate FinFETs fabricated with 193 nm immersion lithography conventional dry etch. fin widths down to 5nm are achieved record ratios 13. Excellent nMOS pMOS is demonstrated for narrow fins short gates. Further improvement in can be by eliminating access resistance that currently attributed poor re-crystallization implantation damage fins. Fully-depleted show strongly improved channel effect (SCE) control when the...
This paper presents a new integration scheme for complementary hetero-junction vertical Tunnel FETs (VTFETs), whereby sacrificial source layer is used during the device fabrication and replaced by final hetero-source materials, respectively n- or p-TFETs, thereby minimizing thermal budget applied to junctions. With demonstration of this source-replacement-last module Ge n-TFET, we show that it possible grow highly doped hetero-junctions on Si channel with steep doping profiles without...
This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: Q factor increased to 25 as compared our previous work, I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 500 μA/ μm at xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> 100 nA/μm achieved, approaching best...
Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal nanowire (NW) demonstrated, the process flow described in this paper can be adjusted to make vertically stacked NWs increase drive per footprint. The short-channel have round 9-nm diameter and GAA smallest channel gate dimensions (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% 45%. show that the performance these devices is substantially improved by high-pressure (HP) deuterium (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) anneal, which ascribed to 2x reduction interface trap density xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ). Furthermore, it found...
We report on Si nanosheet monolithic Complementary Field-Effect Transistors (CFETs) at industry-relevant 48nm gate pitch, with source-drains (SDs) and SD contacts formed for either bottom or top devices. epi patterning 30nm vertical N-P space high-aspect-ratio contact formation are successfully demonstrated. Functional devices excellent subthreshold slope $(SS_{SAT}=7075$ mV/dec) reported devices, both N- PMOS. Middle dielectric isolation (MDI) by SiGe replacement processing is introduced as...
Over the last years there has been lots of interest in use germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility attracted attention application advanced pMOS devices. Indium gallium arsenide compounds, their intrinsically superior electron saturation velocity, are considered a candidate nMOS devices beyond 14 nm node technology.
Uniaxial stressors have received much interest over the last few years as a method to enhance carrier mobility and, hence, drive current with minimal modification structure of transistor. However, shift in device design complex structures multiple crystallographic orientations like advanced bulk-FinFETs has significantly complicated incorporation enhancing stressors. For n-FinFET particular, it turns out that crystal quality and growth rate Si:P Si:C:P films can be strongly dependent upon...
As contact resistance becomes a bottle-neck in scaled CMOS devices, there is need for source/drain epitaxy with maximum dopant concentrations and optimized contacting schemes. In this paper we discuss the use of highly doped Si:P layers Source/Drain formation Si bulk FinFETs. We report on macroscopic microscopic properties details microstructure manifestation Phosphorus-Vacancy complexes at high Phosphorus concentrations. analyze how post-epi thermal budget like spike or laser annealing...
Abstract After a short description of the evolution metal-oxide-semiconductor device architectures and corresponding requirements on epitaxial growth processes, manuscript describes material properties complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations have been grown using conventional process gases. A relatively high temperature is to obtain acceptable Si SiGe rates. Still island has suppressed...
Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time high density 45nm Fin pitch using a replacement channel approach Si substrate. In comparison to our previous work isolated sGe [1], 14/16nm technology node compatible modules such as metal gate and germanide-free local interconnect were implemented. The I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I...
The Ge-source tunnel FETs (TFETs) are fabricated using a novel replacement-source approach, whereby dummy source is replaced at the end of process flow by final material to form an heterojunction. We show that can be successfully while maintaining gate dielectric integrity in gate-source overlap (GS-OL) region and selectively exposed materials. Due situ-doped epitaxial-grown low thermal budget, this integration scheme leads formation highly doped abrupt heterojunction allows complementary...
Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> of 1.3mS/μm at V xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> =-0.5V and good short channel control down to 60nm gate length. Optimization P-doping in SiGe, optimized Si cap passivation thickness Ge, improved wrap all improve device characteristics. The...
Forksheet devices have been recently proposed to further reduce the n-to-p spacing/footprint of transistors on wafer. In this work, we report a systematic comparison DC performance Forksheets and Nanosheets (with relevant dimensions 23nm width 7nm thickness) co-integrated same wafers. It is shown that short channel control transport properties (from Room Temperature up 125°C) are comparable down LG=22nm. We also show gate stack reliability does not suffer from SiN deposition etch back...
In this paper we demonstrate superior NBTI reliability of SiGe pFETs with ultra-thin EOT in a Replacement Metal Gate (RMG) process flow, and channel bulk pFinFET architecture. Moreover, investigate the Forward Body Bias (FBB) technique showing that it can very efficiently improve device I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> without compromising reliability, or vice versa further ION. Based on insights provided by...
Calculations of stress enhanced mobilities are performed for n- and p-FinFETs with both Si Ge channels the 14 nm node beyond. Relaxed even a GeSn5% source / drain stressor cannot outperform strained Si. However, growing channel on SiGe75% strain relaxed buffer (SRB) provides 49% mobility boost over For n-FinFETs, SRB is also possible, SiGe 25% improving by 83%. Addition Si:C 2% S/D increases that benefit to 109%. 120%, owing primarily 6× increase in fin sidewall mobility. Adding 75% 210%. In...
An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SRB/highly-strained Ge pFinFETs are demonstrated down 35 gate length. With a CET <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">INV</inf> -normalized G xmlns:xlink="http://www.w3.org/1999/xlink">M,SAT,INT</inf> of 6.7 nm.mS/µm, Si...
Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> ) of ∼2×10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">−9</sup> Ω·cm xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Si xmlns:xlink="http://www.w3.org/1999/xlink">0.3</inf> Ge xmlns:xlink="http://www.w3.org/1999/xlink">0.7</inf> :B using same Ti based pre-contact amorphization (PCAI) plus...
With the continued scaling of CMOS devices below 10 nm node, process technologies become more and challenging as allowable thermal budget for device processing continuously reduces. This is especially case during epitaxial growth, where a reduction required number potential reasons example to avoid uncontrolled layer relaxation strained layers, surface reflow narrow fin structures, well doping diffusion material intermixing. Further aspects even when Ge used high-mobility channel concept...